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首页> 外文会议>13th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2003; Sep 10-12, 2003; Turin, Italy >Analysis of High-Speed Logic Families
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Analysis of High-Speed Logic Families

机译：高速逻辑系列分析

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摘要

In this paper, we compare the current de-facto standard high-speed family (self-resetting domino logic) with the most promising recently proposed ones: dynamic current mode logic, gate diffusion input logic and race logic architecture. For this purpose, we have used an 8-bit array multiplier in the 0.13 um TSMC CMOS process whose critical path is representative of many modern complex ICs. Each design adopts solely one logic style and it has been optimized with a standard industrial semi-custom flow. As metrics of comparison we have used speed and the energy (E), energy-per-time (ET) and energy-per-time-square (ET2) metrics. The comparison shows that self-resetting domino logic is the best choice when only speed is of concern, while dynamic current mode logic should be the preferred approach for all other cases. The other logic families failed to live up with their original promises of high-performance.
机译：在本文中，我们将当前实际的标准高速系列（自复位多米诺逻辑）与最近提出的最有前途的系列进行了比较：动态电流模式逻辑，门扩散输入逻辑和竞争逻辑架构。为此，我们在0.13 um TSMC CMOS工艺中使用了8位阵列乘法器，其关键路径代表了许多现代复杂IC。每种设计仅采用一种逻辑样式，并已通过标准工业半定制流程进行了优化。作为比较指标，我们使用了速度和能量（E），单位时间能量（ET）和单位时间能量（ET2）指标。比较表明，当仅考虑速度时，自复位多米诺逻辑是最佳选择，而动态电流模式逻辑应该是所有其他情况的首选方法。其他逻辑系列未能履行其对高性能的最初承诺。

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