CMOS Gate Sizing under Delay Constraint

机译：延迟约束下的CMOS栅极尺寸

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In this paper we address the problem of delay constraint distribution on a CMOS combinatorial path. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on the Newton-Raphson like algorithm. Validation is obtained on a 0.25μm process by comparing the different constraint distribution techniques on various benchmarks.

机译：在本文中，我们解决了CMOS组合路径上的延迟约束分布问题。我们首先定义一种方法，可以在任何路径上确定表征该结构的合理延迟范围。然后，我们定义了两种约束分配方法，分别与相等延迟分配和基于牛顿-拉夫森式算法的工业工具进行比较。通过在各种基准上比较不同的约束分布技术，可以在0.25μm的工艺上进行验证。

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《13th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2003; Sep 10-12, 2003; Turin, Italy》|2003年|p.60-69|共10页
会议地点 Turin(IT);Turin(IT)
作者
A. Verle; X. Michel; P. Maurine; N. Azemard; D. Auvergne;
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作者单位

LIRMM, UMR CNRS/Universite de Montpellier II, (C5506), 161 rue Ada, 34392 Montpellier, France;

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原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
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1. A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic [J] . Lowe K.S., Gulak P.G. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1998,第5期

机译：一种用于优化CMOS和BiCMOS组合逻辑中的延迟和功耗的联合栅极大小调整和缓冲器插入方法
2. A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates] [J] . Kasamsetty K., Ketkar M. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2000,第7期

机译：一类新的延迟建模凸函数及其在晶体管尺寸确定中的应用[CMOS gates]
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机译：初始延迟时间的分析和建模及其对CMOS逻辑门的传播延迟的影响
4. CMOS Gate Sizing under Delay Constraint [C] . A. Verle, X. Michel, P. Maurine, International Workshop on Integrated Circuit and System Design . 2003

机译：CMOS栅极尺寸延迟约束
5. Accurate gate delay evaluation of CMOS deep sub-micron VLSI circuits. [D] . Chen, Xian Hong. 2000

机译：CMOS深亚微米VLSI电路的准确栅极延迟评估。
6. Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits [O] . Yiming Li, Chieh-Yang Chen, Min-Hui Chuang, 2019

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7. A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay and Power in CMOS and BiCMOS Combinational Logic [O] . Kerry S. Lowe, P. Glenn Gulak, Senior Member 2015

机译：一种优化CmOs和BiCmOs组合逻辑中延迟和功率的联合栅尺寸和缓冲器插入方法

CMOS Gate Sizing under Delay Constraint

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