New DCT computation algorithm for VLIW architecture

机译：VLIW架构的新DCT计算算法

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摘要

In this paper, a new DCT computation algorithm is presented, which is based on existing fast DCT algorithm and has fully utilized the parallelism of VLIW architecture of DSP to achieve high speed performance. Simulation results show that this method can reduce more than 70% and 20% computing cycles, compared with normal and fast DCT computation algorithm respectively.

机译：本文提出了一种新的DCT计算算法，该算法基于现有的快速DCT算法，充分利用了DSP的VLIW架构的并行性来实现高速性能。仿真结果表明，与常规DCT和快速DCT计算算法相比，该方法可减少70％和20％以上的计算周期。

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来源
《2002 6th International Conference on Signal Processing Proceedings (ICSP'02) Vol.1; Aug 26-30, 2002; Beijing, China》|2002年|p.41-44|共4页
会议地点 Beijing(CN);Beijing(CN)
作者
Li Ji; Li Xue Ming;
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作者单位

School of Information Engineering, BUPT, Beijing, 100876;

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会议组织
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
discrete cosine transform (DCT); very long instruction word (VLIW); parallel;

机译：离散余弦变换（DCT）;超长指令字（VLIW）;并行;

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专利

1. Patent Issued for Fast DCT Algorithm for DSP with VLIW Architecture [J] . Journal of Engineering . 2013,第13期

机译：具有VLIW架构的DSP的快速DCT算法已获专利
2. Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST [J] . Chiper D.F., Swamy M.N.S., Ahmad M.O., IEEE transactions on circuits and systems . I , Regular papers . 2005,第6期

机译：用于DCT / DST / IDCT / IDST计算的统一体系结构的脉动算法和基于内存的设计方法
3. Systolic Algorithms and a Memory-Based Design Approach for a Unified Architecture for the Computation of DCT/DST/IDCT/IDST [J] . Doru Florin Chiper, M. N. S. Swamy, M. Omair Ahmad, IEEE Transactions on Circuits and Systems. I, Regular Papers . 2005,第6期

机译：用于DCT / DST / IDCT / IDST计算的统一体系结构的收缩算法和基于内存的设计方法
4. New DCT computation algorithm for VLIW architecture [C] . Li Ji, Li Xue Ming . 2002

机译：VLIW架构的新DCT计算算法
5. Development of DCT algorithms with DSP architectures in CAE environments. [D] . Ford, Stephen Scott. 1988

机译：在CAE环境中使用DSP架构开发DCT算法。
6. Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures [O] . Haijing Tang, Xu Yang, Siye Wang, 2013

机译：连接寄存器文件的集群式VLIW架构的优化指令调度和寄存器分配
7. A New Hardware-Efficient Algorithm and Architecture for Computation of 2-D DCTs on a Linear Array [O] . Shen-fu Hsiao, Wei-ren Shiue 2001

机译：一种新的硬件高效算法和架构，用于计算线性阵列上的二维DCT

New DCT computation algorithm for VLIW architecture

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