65nm layout enhancement and timing closure analysis

机译：65nm布局增强和时序收敛分析

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摘要

In this paper, Recommended Design for Manufacture (RDFM) flow is proposed including dummy metal fill, redundant VIAs insertion, layout enhancement, dummy PO/OD insertion to improve chip yield. This flow is targeted at 65nm process. Due to the layout modification imported by RDFM, timing signoff closure is analyzed. Results show that RDFM flow imports about 5% clock period uncertainty to the design.

机译：本文提出了制造推荐设计（RDFM）流程，包括虚拟金属填充，冗余VIA插入，布局增强，虚拟PO / OD插入，以提高芯片良率。该流程针对65nm工艺。由于RDFM导入了布局修改，因此分析了时序签收关闭。结果表明，RDFM流为设计带来了大约5％的时钟周期不确定性。

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来源
《2012 international conference on future communication and computer technology》|2012年|37-41|共5页
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作者
Gang Zhao; Ligang Hou; Jiahui Zhu; Wuchen Wu; Steve Knepper;
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作者单位

Beijing University of Technology, Chaoyang District, Beijing, China;

Beijing University of Technology, Chaoyang District, Beijing, China;

Beijing University of Technology, Chaoyang District, Beijing, China;

Beijing University of Technology, Chaoyang District, Beijing, China;

804 Woburn Street, Boston, Massachusetts, U.S.;

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原文格式 PDF
正文语种 eng
中图分类计算技术、计算机技术;
关键词
Design for Manufacture; 65nm; Layout enhancer; Timing closure;

机译：制造设计; 65nm;布局增强器;定时闭合;

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65nm layout enhancement and timing closure analysis

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