A 6.25Gbps Feed-forward Equalizer in 0.18#x03BC;m CMOS Technology for SerDes

机译：采用0.18μmCMOS技术的6.25Gbps前馈均衡器，用于SerDes

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This paper presents a 6.25Gbps feed-forward equalizer (FFE) to reduce the inter-symbol-interference (ISI) in high-speed transmission backplane. The 3-tap fractionally spaced equalizer consists of a delay line, multiplier & summer cells and an output circuit. Active-inductive peaking circuit and capacitor-degenerated circuit are used in the delay line and the output stage respectively to meet the bandwidth demand. The proposed FFE has been implemented in TSMC 0.18μm CMOS technology with a whole area of 0.5mm×0.51mm including I/O pads. The power consumption of the core circuit is 31.7mW under 1.8V power supply. Post simulation results show that the distorted signal through a 24-inch backplane is well recovered by this equalizer.

机译：本文提出了一种6.25Gbps前馈均衡器（FFE），以减少高速传输背板中的符号间干扰（ISI）。 3抽头的分数间隔均衡器由延迟线，乘法器和求和单元以及一个输出电路组成。延迟线和输出级分别使用有源电感峰值电路和电容器退化电路，以满足带宽需求。拟议的FFE已在TSMC0.18μmCMOS技术中实现，包括I / O焊盘在内的整个面积为0.5mm×0.51mm。在1.8V电源下，核心电路的功耗为31.7mW。后期仿真结果表明，通过该均衡器可以很好地恢复通过24英寸底板的失真信号。

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来源
《2012 International Conference on Wireless Communications amp; Signal Processing》|2012年|1-4|共4页
会议地点 Huangshan(CN)
作者
Gao Jian; Hu Qing-Sheng;
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作者单位

Institute of RF- OE-ICs, Southeast University Nanjing, 210096, Chinac;

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原文格式 PDF
正文语种 eng
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关键词
active-inductive peaking; capacitor-degenerated; current mode logic (CML); delay line cell; feed-forward equalizer (FFE); fractionally spaced equalizer (FSE);

机译：有源电感峰值;电容器退化;电流模式逻辑（CML）;延迟线单元;前馈均衡器（FFE）;小间距均衡器（FSE）;;

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1. A 6.4-Gb/s CMOS SerDes Core With Feed-Forward and Decision-Feedback Equalization [J] . Troy Beukema, Michael Sorna, Karl Selander, IEEE Journal of Solid-State Circuits . 2005,第12期

机译：具有前馈和决策反馈均衡功能的6.4 Gb / s CMOS SerDes内核
2. A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology [J] . Shuai Yuan, Liji Wu, Ziqiang Wang, IEEE transactions on circuits and systems . I , Regular papers . 2016,第7期

机译：70 mW 25 Gb / s四分之一速率SerDes发送器和接收器芯片组，采用65 nm CMOS技术，具有40 dB的均衡
3. A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes [J] . Zhang Mingke, Hu Qingsheng Journal of Semiconductors . 2013,第12期

机译：采用0.18μmCMOS技术的6.25 Gb / s均衡器，用于高速SerDes
4. A 6.25Gbps Feed-forward Equalizer in 0.18#x03BC;m CMOS Technology for SerDes [C] . Gao Jian, Hu Qing-Sheng International Conference on Wireless Communications Signal Processing . 2012

机译：用于SERDES的0.18μmCMOS技术中的6.25GMGPS前馈均衡器
5. Adaptive analog equalization of multimode fiber channels using 0.13mum CMOS technology. [D] . Kargar, Mahyar. 2009

机译：采用0.13mum CMOS技术的多模光纤通道的自适应模拟均衡。
6. A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor [O] . Seokwon Choi, Changmin Song, Young-Chan Jang 2021

机译：一个3.0 Gsymbol / S / Lane MIPI C-PHY接收器具有用于移动CMOS图像传感器的自适应电平依赖性均衡器
7. Design and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technology [O] . Conde-Almada Ernesto 2016

机译：130nm CMOS技术的片上SerDes系统模拟接收器的设计和物理实现

A 6.25Gbps Feed-forward Equalizer in 0.18#x03BC;m CMOS Technology for SerDes

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