SoC performance evaluation with ArchC and TLM-2.0

机译：使用ArchC和TLM-2.0进行SoC性能评估

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ArchC is an architecture description language that provides instruction set level simulation and binary tool chain generation. It is based on SystemC and can communicate with other SystemC components using transaction level modeling (TLM). In this article we present an upgrade of ArchC that allows TLM-2.0 usage and makes it available in timed simulations. These extensions enable performance evaluation of complete System-on-Chip designs built around an ArchC processor model. As a proof-of-concept, we examine various TLM-connected memory hierarchies. We outline how model designers can use a combination of fast functional simulation and slow timed simulation to determine an optimal system architecture for a given workload.

机译：ArchC是一种体系结构描述语言，可提供指令集级仿真和二进制工具链生成。它基于SystemC，并且可以使用事务级别建模（TLM）与其他SystemC组件进行通信。在本文中，我们介绍了ArchC的升级版本，该版本允许使用TLM-2.0，并可以在定时仿真中使用。这些扩展可对基于ArchC处理器模型构建的完整片上系统设计进行性能评估。作为概念验证，我们研究了各种TLM连接的内存层次结构。我们概述了模型设计人员如何结合快速功能仿真和慢时仿真来确定给定工作负载的最佳系统架构。

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来源
《2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip》|2013年|1-8|共8页
会议地点 Darmstadt(DE)
作者
Walter; Jorg; Lenhardt; Jorg; Schiffmann; Wolfram;
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作者单位

OFFIS Institute for Information Technology, Oldenburg, Germanyc;

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原文格式 PDF
正文语种 eng
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关键词
ADL; system-on-chip; transaction level modeling;

机译：ADL;片上系统;事务级别建模;;

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SoC performance evaluation with ArchC and TLM-2.0

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