• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip >Exploiting FPGA block memories for protected cryptographic implementations
【24h】

Exploiting FPGA block memories for protected cryptographic implementations

机译：利用FPGA块存储器实现受保护的密码实现

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security.
机译：现代现场可编程门阵列（FPGA）具有强大的功能，可简化设计人员。诸如大块存储器（BRAM），数字信号处理（DSP）内核，嵌入式CPU等功能的可用性使FPGA的设计策略与ASIC截然不同。 FPGA还广泛用于对安全性至关重要的应用，在这些应用中，防范已知攻击至关重要。我们专注于针对物理实施的物理攻击。为了设计针对此类攻击的对策，FPGA设计人员的策略也应与ASIC中的策略不同。应该利用可用的功能来设计紧凑而强大的对策。在本文中，我们提出了利用FPGA中的BRAM设计紧凑对策的方法。 BRAM可用于优化诸如屏蔽和双轨逻辑之类的内在对策，否则它们会产生大量开销（至少2倍）。该优化应用在真实的AES-128协处理器上，并在Xilinx Virtex-5芯片上进行了面积开销和电阻测试。当应用于AES时，提出的掩蔽对策仅具有16％的开销。此外，双轨预充电逻辑（DPL）对策已经过优化，可以将整个顺序部分打包在BRAM中，从而增强了安全性。进行适当的鲁棒性评估以分析区域和安全性的优化。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号