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首页> 外文会议>2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip >Dynamically reconfigurable FIR filter architectures with fast reconfiguration
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Dynamically reconfigurable FIR filter architectures with fast reconfiguration

机译：具有快速重新配置功能的动态可重新配置FIR滤波器架构

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摘要

This work compares two finite impulse response (FIR) filter architectures for FPGAs for which the coefficients can be reconfigured during run-time. One is a recently proposed filter architecture based on distributed arithmetic (DA) and the other is based on a LUT multiplication scheme. Instead of using the common internal configuration access port (ICAP) for reconfiguration which is able to change the logic as well as the routing, it is sufficient to reconfigure only the logic in the regarded architectures. This is realized by using the configurable look-up table (CFGLUT) primitive of Xilinx that allows reconfiguration times which are orders of magnitudes faster than using ICAP. The resulting FIR filter architectures achieves reconfiguration times of typically less than 100 ns. They can be reconfigured with arbitrary coefficients that are only limited by their length and word size. As their resource consumptions depend on different parameters of the filter, a detailed comparison is done. It turned out that if the input word size is greater than approximately half the number of coefficients, the LUT based multiplication scheme needs less resources than the DA architecture and vice versa.
机译：这项工作比较了FPGA的两种有限冲激响应（FIR）滤波器架构，可以在运行时对其系数进行重新配置。一种是最近提出的基于分布式算术（DA）的滤波器体系结构，另一种是基于LUT乘法方案的。与其使用能够更改逻辑和路由的公用内部配置访问端口（ICAP）进行重新配置，仅在所考虑的体系结构中重新配置逻辑就足够了。这是通过使用Xilinx的可配置查找表（CFGLUT）原语实现的，该原语允许的重新配置时间比使用ICAP快几个数量级。最终的FIR滤波器架构实现的重新配置时间通常少于100 ns。可以使用任意系数重新配置它们，这些系数仅受其长度和字长限制。由于它们的资源消耗取决于过滤器的不同参数，因此需要进行详细的比较。事实证明，如果输入字大小大于系数数量的一半，则基于LUT的乘法方案所需的资源少于DA架构，反之亦然。

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