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首页> 外文会议>2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip >Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction
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Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction

机译：通过利用动态路由延迟预测来提高并行MPSoC仿真性能

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摘要

Raising the abstraction level or parallel execution are two possible solutions in order to cope with extremely long runtimes of complex Multi-Processor System-on-Chip (MPSoC) simulations. Within previous works, a SystemC/TLM based modeling methodology targeting accurate simulation of NoC-based MPSoCs bas been proposed that benefits from both. Communication is abstracted into transactions. This enables extraction of parallelism through temporal decoupling for increasing efficiency of parallel simulation if a loss of accuracy is acceptable. This work extends previous works by a dynamic prediction mechanism that allows adapting the degree of temporal decoupling during runtime and thus prevents any loss of accuracy. The method is based on local time quanta that exist once for every module connection. Delay annotations within modules are exploited for predicting communication delays between modules. Based on these predictions, local time quanta are dynamically adjusted. The approach is evaluated by means of a realistic MPSoC model. Measurements have been performed on different host platforms. Results demonstrate that the method can significantly contribute to acceleration of parallel and sequential simulation.
机译：提高抽象级别或并行执行是两种可能的解决方案，以应对复杂的多处理器片上系统（MPSoC）仿真的极长运行时间。在先前的工作中，提出了一种基于SystemC / TLM的建模方法，该方法针对基于NoC的MPSoC的精确仿真，这两者都受益。通信被抽象为交易。如果可以接受精度损失，则可以通过时间去耦来提取并行性，以提高并行仿真的效率。这项工作通过动态预测机制扩展了以前的工作，该机制允许在运行时调整时间解耦的程度，从而防止精度损失。该方法基于每个模块连接都存在一次的本地时间量。利用模块内的延迟注释来预测模块之间的通信延迟。基于这些预测，可以动态调整本地时间量。该方法是通过实际的MPSoC模型进行评估的。测量是在不同的主机平台上执行的。结果表明，该方法可以极大地促进并行和顺序仿真的加速。

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