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首页> 外文会议>2013 IEEE Conference on Reliability Science for Advanced Materials and Devices >The effect of etch residuals on via reliability
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The effect of etch residuals on via reliability

机译：蚀刻残留物对通孔可靠性的影响

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摘要

Vias are formed in interconnect structures using a polymerizing chemistry in order to avoid etching the underlying metal wires. However, a drawback of the polymerizing chemistry is that etch residues can remain in the via opening, resulting in high via resistance and possible degradation of circuit performance. Although it is well known that etch residues in vias can cause yield loss, the effect on reliability has not been reported for submicron vias. In this paper, the effect of etch residues on via reliability is studied. Vias with etch residues showed no degradation in reliability after a thermal cycle stress, high temperature storage, or humidity stress. However, vias with etch residues fail at a lower current during a wafer level voltage ramp electromigration stress, compared to residue-free vias, suggesting that etch residues will reduce the electromigration lifetime of interconnect structures.
机译：为了避免蚀刻下面的金属线，使用聚合化学方法在互连结构中形成过孔。然而，聚合化学的缺点是蚀刻残留物会残留在通孔开口中，导致高通孔电阻并可能降低电路性能。尽管众所周知，通孔中的蚀刻残留物会导致成品率下降，但尚未报道过亚微米通孔对可靠性的影响。在本文中，研究了蚀刻残留物对通孔可靠性的影响。经过热循环应力，高温存储或湿度应力后，具有蚀刻残留物的通孔的可靠性没有降低。然而，与无残留物的通孔相比，具有蚀刻残留物的通孔在晶圆级电压斜坡电迁移应力期间在较低的电流下会失效，这表明蚀刻残留物会缩短互连结构的电迁移寿命。

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