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首页> 外文会议>2013 International Conference on Circuits, Power and Computing Technologies >Low power, high speed hybrid clock divider circuit
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Low power, high speed hybrid clock divider circuit

机译：低功耗，高速混合时钟分频器电路

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摘要

The Clock Divider circuit has found immense application in Multiple Clock Domain (MCD) systems like ASICs, SoC and GALS. In MCD systems, we generate many clock signals of various frequencies from a high frequency clock by frequency division. Power is an important parameter to be minimized since the nodes in a clock divider circuit will toggle at clock frequency. In this paper, we present a low power hybrid clock divider circuit which can take an input frequency up to 6 GHz and perform frequency division. The divider is hybrid because it uses two different flip flops - a Modified Extended True Single-Phase Clock flip flop (METSPC-FF) and a self blocking FF (SBFF).The METSPC-FF is fast enough to divide a GHz frequency, but consumes more power when compared to SBFF, while the SBFF is relatively slow but consumes less power compared to METSPC. We analyze the performance of these 2 FFs across PVT variations and implement them in a clock divider circuit. Our clock divider circuit consumes 149.56 µW power for ‘divide by’ 8 operation on a 6 GHz clock. Simulation of these flip flops in TSMC 90 nm technology using CADENCE SPECTRE simulator shows that they are very energy efficient and hence can be used for other high speed applications without compromising on the power.
机译：时钟分频器电路已在ASIC，SoC和GALS等多时钟域（MCD）系统中得到了广泛的应用。在MCD系统中，我们通过分频从高频时钟生成许多不同频率的时钟信号。功率是一个需要最小化的重要参数，因为时钟分频器电路中的节点将以时钟频率触发。在本文中，我们提出了一种低功耗混合时钟分频器电路，该电路可以采用高达6 GHz的输入频率并进行分频。该分频器是混合式的，因为它使用了两个不同的触发器-修改后的扩展式真单相时钟触发器（METSPC-FF）和自阻塞FF（SBFF）.METSPC-FF的速度足以划分GHz频率，但是与SBFF相比，其功耗更高，而SBFF相对较慢，但与METSPC相比功耗更低。我们分析了PVT变化中这2个FF的性能，并在时钟分频器电路中实现它们。我们的时钟分频器电路在6 GHz时钟上进行“除以8”操作时消耗149.56 µW功率。使用CADENCE SPECTER模拟器在TSMC 90 nm技术中对这些触发器进行仿真显示，它们具有很高的能效，因此可以在不影响功耗的情况下用于其他高速应用。

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