Optimization of doping profile and isolation oxide thickness in bulk FinFETs using TCAD simulations

机译：使用TCAD仿真优化块FinFET中的掺杂分布和隔离氧化物厚度

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The effect of doping profile of channel stop implant underneath the fin for optimum thickness of isolation oxide corresponding to minimum IOFF, maximum ION and maximum ION/IOFF has been studied in 65nm Bulk FINFET by device simulations in TCAD. Studies are done by varying the peak position of doping concentration and position at which it equals substrate concentration with respect to substrate height for isolation oxide thickness varying from 10–100 nm. Performance metrics used are minimum IOFF, maximum ION and maximum ION/IOFF. The optimized isolation oxide thickness for minimum IOFF, is observed at 10 nm with position of peak doping concentration at minimum alpha and maximum sigma.

机译：鳍片下方沟道停止注入的掺杂分布对隔离氧化物的最佳厚度的影响，该厚度对应于最小I OFF ，最大I ON 和最大I ON / I OFF 。通过改变掺杂浓度的峰值位置和其相对于基板高度的等于基板浓度的位置来完成研究，隔离氧化物的厚度在10-100 nm之间变化。使用的性能指标为最小I OFF ，最大I ON 和最大ION / I OFF 。在10 nm处观察到最小I OFF 的最佳隔离氧化物厚度，峰值掺杂浓度在最小alpha和最大sigma位置。

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来源
《2013 International Conference on Circuits, Power and Computing Technologies》|2013年|959-965|共7页
会议地点 Nagercoil(IN)
作者
Scarlet Priscilla; Nagarajan K.K.; Srinivasan R.;
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作者单位

ECE Department, SSN College of Engineering, Chennai, Indiac;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Bulk FinFET; Doping Profile; Isolation oxide thickness; TCAD;

机译：体FinFET;掺杂分布;隔离氧化物厚度; TCAD;;

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1. Optimization of Gate - Source/Drain Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations [J] . K. K. NAGARAJAN, N. VINODHKUMAR, R. SRINIVASAN WSEAS Transactions on Circuits and Systems . 2012,第10a12期

机译：基于TCAD仿真的基于30 nm栅极长度FinFET的LNA优化栅源/漏重叠
2. Heavy-ion irradiation study in SOI-based and bulk-based junctionless FinFETs using 3D-TCAD simulation [J] . Vinodhkumar N., Bhuvaneshwari Y. V., Nagarajan K. K., Microelectronics & Reliability . 2015,第12PTaB期

机译：使用3D-TCAD模拟在基于SOI和基于体的无结FinFET中进行重离子辐照研究
3. Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation [J] . Nilamani S., Ramakrishnan V. N. Journal of Computational Electronics . 2017,第1期

机译：基于3D TCAD仿真的基于20nm FinFET和无结FinFET的6T-SRAM电路的栅极和漏极SEU灵敏度
4. Optimization of doping profile and isolation oxide thickness in bulk FinFETs using TCAD simulations [C] . Scarlet Priscilla, Nagarajan K.K., Srinivasan R. International Conference on Circuits, Power and Computing Technologies . 2013

机译：用TCAD模拟优化料料掺杂型材和分离氧化物厚度
5. An Optimized TCAD Simulation of a Low-Power, High-Frequency Lateral SiGe HBT on SOI Device [D] . Peterson, Amelia H. 2017

机译：SOI设备低功耗，高频横向SiGE HBT的优化TCAD模拟
6. Performance Optimization of FD-SOI Hall Sensors Via 3D TCAD Simulations [O] . Linjie Fan, Jinshun Bi, Kai Xi, 2020

机译：通过3D TCAD模拟FD-SOI霍尔传感器的性能优化
7. Device optimization of bulk FinFETs and its comparison with SOI FinFETs [O] . MANOJ CR, MEENAKSHI N, DHANYA V, 2007

机译：体FinFET的器件优化及其与SOI FinFET的比较
8. Effect of Annealing and Oxide Layer Thickness on Doping Profiles Shape of ''Through-Oxide'' Implanted P sup + Ions in Textured Silicon. [R] . El-Dessouki, M. S., Galloni, R. 1987

机译：退火和氧化层厚度对织构硅中“穿透氧化物”注入p sup +离子掺杂分布形状的影响。

Optimization of doping profile and isolation oxide thickness in bulk FinFETs using TCAD simulations

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