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首页> 外文会议>2013 International Conference on Circuits, Power and Computing Technologies >Design of high performance folded DIF FFT architecture using MMCM approach with Hcub algorithm
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Design of high performance folded DIF FFT architecture using MMCM approach with Hcub algorithm

机译：使用Hcub算法的MMCM方法设计高性能折叠DIF FFT架构

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This paper propose the high performance FFT architecture by minimization of power using the Multiplier less Multiple Constant Multiplication (MMCM) approach. In the recent applications, hardware engineers have continuously tried to design a well-organized FFT architecture in an efficient manner. In the proposed architecture has the MCM system in which the multiplier can be replaced by using the adders/subtractors and the shifts operations. The addition and shift operations that realize the complex multiplication with the help of Heuristic Cumulative Benefit (Hcub) algorithm and it uses folding transformation which reduces the power consumption in the architecture. FFT architecture has a butterfly structure which act as a important part in the multiplications by constants, this can be reduced by using the MCM approach. Thus, the MCM with Hcub algorithm in the butterflies can effectively reduce the number of real as well as imaginary multiplications by constants. Thus the folded FFT hardware architectures with are widely used for low area and low power consumption overall which produce high performance architecture.
机译：本文提出了一种高性能的FFT架构，它使用无乘子多重常数乘法（MMCM）方法将功耗降至最低。在最近的应用中，硬件工程师一直在尝试以高效的方式设计井井有条的FFT架构。在所提出的架构中，具有MCM系统，其中可以通过使用加法器/减法器和移位运算来替换乘法器。加法和移位运算借助启发式累积效益（Hcub）算法实现了复杂的乘法运算，并且使用折叠变换来减少体系结构中的功耗。 FFT体系结构具有蝶形结构，该结构在乘以常数的过程中起着重要的作用，可以通过使用MCM方法来减少这种结构。因此，蝴蝶中具有Hcub算法的MCM可以有效地减少常数的实数和虚数乘法。因此，折叠式FFT硬件体系结构被广泛用于产生高性能体系结构的总体上较小的面积和较低的功耗。

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