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首页> 外文会议>2013 International Conference on Circuits, Power and Computing Technologies >Generic modified Baugh Wooley multiplier
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Generic modified Baugh Wooley multiplier

机译：通用修正的Baugh Wooley乘数

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摘要

In this paper the structural pattern required to create a generic HDL code for a fast Baugh Wooley multiplier has been described. The ripple carry adder in the final stage of the conventional Baugh Wooley multiplier was replaced by a Linear Carry Select Adder, resulting in a modified Baugh Wooley architecture. The post-synthesis results of the multiplier architecture generated by the synthesis tool for HDL defined multiplication statement was compared with the synthesis results of conventional and as well as the modified Baugh Wooley multipliers for different operand sizes ranging from N=4 to N=60 using 90 nm technology library. The post synthesis results for characteristic parameters such as propagation delay, area and power consumption are compared. The comparison shows that the modified Baugh Wooley architecture is faster than the conventional architecture and the architecture generated by the synthesis tool for HDL defined multiplication statement. The speed improvement becomes significant for larger operand sizes.
机译：在本文中，已经描述了为快速的Baugh Wooley乘法器创建通用HDL代码所需的结构模式。传统的Baugh Wooley乘法器最后阶段的纹波进位加法器被线性进位选择加法器取代，从而改进了Baugh Wooley架构。将合成工具针对HDL定义的乘法语句生成的乘法器体系结构的合成后结果与使用N = 4到N = 60的不同操作数大小的常规和改进的Baugh Wooley乘法器的合成结果进行了比较，使用90 nm技术库。比较了诸如传播延迟，面积和功耗等特征参数的合成后结果。比较表明，修改后的Baugh Wooley体系结构比常规体系结构和综合工具为HDL定义的乘法语句生成的体系结构更快。对于较大的操作数大小，速度的提高变得非常重要。

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