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首页> 外文会议>2014 7th International Conference on Information and Automation for Sustainability >Development of a Field programmable GATE array based computer to controller area network store and forward buffer
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Development of a Field programmable GATE array based computer to controller area network store and forward buffer

机译：开发基于现场可编程门阵列的计算机，用于控制器局域网存储和转发缓冲区

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In this paper the development of a Field programmable Gate Array (FPGA) based general purpose computer to Controller Area Network (CAN) store and forward buffer is being discussed. This buffer will read from the incoming data from the computer as bytes and collect and combine them to form the CAN frame and post it to the CAN network for transmission. In the process of development, CAN message frame architecture, voltage levels and bit coding principles were studied extensively. For the experiments and implementation of the designed buffer a developer board with Xilinx Spartan 3E FPGA which has 1920 Configurable Logic Blocks (CLB) was used. Computer to FPGA communications is carried out using RS-232 serial communications. 136 bit long CAN frame is built on the computer and separated to 17 bytes and forwarded to the FPGA. The FPGA assembles it and posts the frame to the network. In this implementation, from the available total, 315 flip flops and 569 look up tables (LUT) were used. From these 443 were used as logic, 126 were used as route through and 1 was used as a shift register. Since the usage of the RS-232 protocol a communication bottleneck makes rise to a delay of 14.1667 ms per frame sent from computer to the FPGA. This delay can be reduced by using Universal Serial Bus (USB) protocols to communicate with the computer. Even though this implementation is for the low speed fault tolerant CAN, speeds can be customized to suit the requirement by varying the frequency of clock ticks, given that the hardware supports such frequencies. As further research this store and forward buffer can be improved to receive acknowledgments from other nodes of the network.
机译：本文讨论了基于现场可编程门阵列（FPGA）的通用计算机到控制器局域网（CAN）存储和转发缓冲区的开发。该缓冲区将从计算机中以字节为单位的传入数据中读取，并收集和组合它们以形成CAN帧并将其发布到CAN网络进行传输。在开发过程中，对CAN消息帧架构，电压电平和位编码原理进行了广泛的研究。为了对设计的缓冲器进行实验和实现，使用了具有Xilinx Spartan 3E FPGA的开发板，该开发板具有1920个可配置逻辑块（CLB）。计算机到FPGA的通信使用RS-232串行通信进行。在计算机上建立了136位长的CAN帧，并将其分隔为17个字节并转发到FPGA。 FPGA对其进行组装并将框架发布到网络。在该实现中，从可用总数中，使用了315个触发器和569个查找表（LUT）。这些443被用作逻辑，126被用作路由，1被用作移位寄存器。由于使用了RS-232协议，因此通信瓶颈导致从计算机发送到FPGA的每帧延迟为14.1667 ms。通过使用通用串行总线（USB）协议与计算机进行通信，可以减少此延迟。即使此实现是针对低速容错CAN的，但只要硬件支持这样的频率，就可以通过更改时钟滴答的频率来定制速度以满足要求。随着进一步的研究，可以改善该存储和转发缓冲区，以接收来自网络其他节点的确认。

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