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首页> 外文会议>2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference: Challenges of Change - Shaping the Future, 16th International Conference on Electronic Materials and packaging >High speed SerDes design verification
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High speed SerDes design verification

机译：高速SerDes设计验证

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摘要

Serial data (SerDes) link has been widely used in gigabit rate link, storage applications, telecom, data communications, etc. The ability to accurately predict SerDdes channel insertion loss and return loss plays a critical role in prediction of SerDes link performance. Two test vehicles are designed to demonstrate the step-by-step modeling technique. One is the bare package sample, and the other is the package on print circuit board (PCB) sample. In this paper, the SerDes signals are designed on both test vehicles and characterized through model to measurement correlation in section I. Section II shows the step-by-step modeling procedure to correlate SerDes model with measurement on bare package sample and the step-by-step modeling technique is validated up to 19 GHz. In section III, the details of measurement technique are discussed in order to guarantee the accuracy of measured data. In section IV, we present the SerDes design reference for operating at 5 GHz and 12.5 GHz depend on the differential insertion loss and near-end coupling performance of bare package and package on PCB in this study. Final are conclusions.
机译：串行数据（SerDes）链路已广泛用于千兆速率链路，存储应用，电信，数据通信等。准确预测SerDdes通道插入损耗和回波损耗的能力在预测SerDes链路性能中起着至关重要的作用。设计了两个测试工具来演示分步建模技术。一种是裸包装样品，另一种是印刷电路板（PCB）上的包装样品。在本文中，SerDes信号在两种测试车辆上均经过设计，并在第一部分中通过模型与测量的相关性进行了表征。第二部分显示了将SerDes模型与裸包装样品的测量相关的分步建模过程，以及分步进行。逐步建模技术已通过验证，最高可达19 GHz。第三部分讨论了测量技术的细节，以保证测量数据的准确性。在第四部分中，我们提供了在5 GHz和12.5 GHz下工作的SerDes设计参考，该参考取决于本研究中裸封装和PCB封装的差分插入损耗和近端耦合性能。最后是结论。

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