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首页> 外文会议>2014 First International Conference on Computational Systems and Communications >Accelerating functional verification of PCI express endpoint by emulating host system using PCI express core
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Accelerating functional verification of PCI express endpoint by emulating host system using PCI express core

机译：通过使用PCI Express内核模拟主机系统来加速PCI Express端点的功能验证

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PCI Express is a high-performance I/O bus protocol. The PCI Express protocol provides higher bandwidth than the legacy buses that makes PCI Express as an ideal choice for a wide variety of applications such as Network Interface, Graphics Accelerators, and Storage Controllers (SSD). The PCI Express protocol supports many features to improve performance of I/O Bus, so verification of a design based on this protocol is a very long and time consuming process. As an application based on the PCI Express protocol becomes more and more complex the verification complexity increases many folds. PCI Express Endpoint device communicates with the host (Processor/Memory) using the Host Interface logic. This logic plays a vital role as it can affect the overall performance of the Endpoint device. The Host Interface logic is protocol specific and responsible for the data transfer from host to device and vice versa. Strategically, as this logic is very crucial, it has to be verified properly. There are multiple ways to verify the host interface logic. However, there is a trade-off between design development time (including verification time) and overall cost. In this paper we present a novel approach to verify the Host Interface Logic. Our method uses a PCI Express core that will act as the Root Complex connected to the Host Interface Logic, i.e. Design Under Test (DUT), this will help to minimize overall design development time by reducing verification time.
机译：PCI Express是一种高性能的I / O总线协议。 PCI Express协议提供了比传统总线更高的带宽，这使PCI Express成为网络接口，图形加速器和存储控制器（SSD）等各种应用程序的理想选择。 PCI Express协议支持许多功能以提高I / O总线的性能，因此基于该协议的设计验证是一个非常漫长且耗时的过程。随着基于PCI Express协议的应用程序变得越来越复杂，验证复杂性也增加了许多倍。 PCI Express端点设备使用主机接口逻辑与主机（处理器/内存）进行通信。该逻辑起着至关重要的作用，因为它会影响Endpoint设备的整体性能。主机接口逻辑是特定于协议的，负责从主机到设备的数据传输，反之亦然。从策略上讲，由于此逻辑非常重要，因此必须正确验证。有多种方法可以验证主机接口逻辑。但是，在设计开发时间（包括验证时间）和总成本之间需要权衡。在本文中，我们提出了一种新颖的方法来验证主机接口逻辑。我们的方法使用PCI Express内核，该内核将充当连接到主​​机接口逻辑（即被测设计（DUT））的根联合体，这将通过减少验证时间来帮助缩短总体设计开发时间。

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