• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>2014 International Conference on Advances in Energy Conversion Technologies : Intelligent Energy Management: Technologies and Challenges >Low power noise tolerant domino 1-bit full adder
【24h】

Low power noise tolerant domino 1-bit full adder

机译：低功耗容忍多米诺1位全加法器

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

A new low power dynamic CMOS one bit full adder cell is presented in this paper. In this design technique is based on semi-domino logic. This new adder cell was compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay product and leakage performance of low voltage full adder cells in different CMOS logic styles. Simulation results demonstrate the superiority of the proposed adder circuit against the pre-proposed adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP, and noise tolerance. The performance of the adder circuits is based on UMC 180nm CMOS process models at the supply voltage of 1.8V evaluated by the comparing of the simulation results obtained from Cadence specter. Simulation results tell that the proposed circuit exhibits a lower PDP and is faster when it was compared with available 1-bit full adder circuits.
机译：本文提出了一种新型的低功耗动态CMOS 1位全加法器单元。在这种设计技术中是基于半多米诺逻辑的。将该新的加法器单元与先前提出的一些广泛使用的动态加法器以及其他常规体系结构进行了比较。这项工作的目的是检查不同CMOS逻辑样式的低压全加器单元的功率，延迟，功率延迟乘积和泄漏性能。仿真结果证明了所提出的加法器电路在功率，延迟，PDP方面优于预先提出的加法器电路。所提出的样式在功率，延迟，PDP和噪声容忍度方面都受益匪浅。加法器电路的性能基于在1.8V供电电压下的UMC 180nm CMOS工艺模型，通过比较从Cadence Spectre获得的仿真结果进行评估。仿真结果表明，与可用的1位全加法器电路相比，该电路的PDP较低，速度更快。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号