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Modeling and analysis of TSV noise coupling and suppression methods for 20nm node and beyond

机译:用于20nm及以上节点的TSV噪声耦合和抑制方法的建模和分析

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摘要

With the technology nodes keep advancing, the application of TSV(Through Silicon Via) technology in 3D integration is faced with more challenges. The shift from via-last to via-middle fabrication scheme, the ever-increasing density of TSV, the reduction in supply voltage and the increase in frequency of on-chip local clock, all pose threat to signal/power integrity of the TSV system. In this paper, the noise coupling effect between TSVs and corresponding suppression methods were modeled and analyzed. Effect of variations of structural parameters on noise coupling are investigated and results are explained based on specifications of advanced technology node. In order to alleviate noise effect under fine pitch scenario, different noise suppression methods are discussed and compared. The guard-ring didn't demonstrate much noise reduction over the whole frequency spectrum, with slightly better performance within the low frequency range. The buried oxide layer of SOI technology also showed little suppression effect in blocking substrate noise. However, the TSV array scheme is significantly effective in noise suppression over the whole frequency spectrum.
机译:随着技术节点的不断发展,TSV(穿透硅过孔)技术在3D集成中的应用面临着更多的挑战。从过孔制造到过孔制造的转变,TSV密度的不断提高,电源电压的降低以及片上本地时钟频率的增加,都对TSV系统的信号/电源完整性构成了威胁。本文对TSV之间的噪声耦合效应及相应的抑制方法进行了建模和分析。研究了结构参数变化对噪声耦合的影响,并根据先进技术节点的规范对结果进行了解释。为了减轻细调情况下的噪声影响,讨论并比较了不同的噪声抑制方法。保护环在整个频谱上并未显示出很大的降噪效果,在低频范围内的性能稍好。 SOI技术的掩埋氧化物层在阻挡衬底噪声方面也表现出很小的抑制作用。但是,TSV阵列方案在整个频谱上的噪声抑制方面非常有效。

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