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Passive equalizer design on high density interconnects for 25Gbps high speed IO and beyond

机译:高密度互连上的无源均衡器设计,可实现25Gbps高速IO及更高速率

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摘要

We propose a passive equalizer design on high density interconnects to improve the serial chip-to-chip communication channel performance. This new technique is a novel implementation and reinvention of the quarter-wave impedance transformer design originally adopted in the RF/microwave systems. By using narrow traces at early escaping routing and series of fat section impedance compensators at periodic λ/4 distances, this technique relies heavily on the signal wavelength of operating frequency and is suitable for specific high speed systems as required by PCIe, QPI, KTI, and SerDes for 25GHz and beyond. This technology utilizes the frequency-selective structures and has been tested on both microstrip and stripline routing of a flip-chip package design. Using proposed design optimization process for passive equalizer, we can maximize eye-opening and minimize inter-symbol interference in order to reduce data-dependent jitter. For 25Gbps differential high speed signaling, it shows over 3.1 dB improvement on differential return loss and over 0.7 dB improvement on differential insertion loss, which translate to over 17% increase on eye height and over 7% decrease of jitter for end-to-end whole channel simulation on server blade.
机译:我们提出了一种在高密度互连上的无源均衡器设计,以改善串行芯片间通信通道的性能。这项新技术是对最初在RF /微波系统中采用的四分之一波阻抗变压器设计的新颖实现和创新。通过在较早的转义路径上使用狭窄的迹线以及在周期性的λ/ 4距离处使用一系列的胖段阻抗补偿器,该技术在很大程度上依赖于工作频率的信号波长,适用于PCIe,QPI,KTI,以及25GHz及更高​​频率的SerDes。该技术利用了频率选择结构,并且已经在倒装芯片封装设计的微带和带状线布线上进行了测试。使用针对无源均衡器的拟议设计优化过程,我们可以最大程度地张开眼睛并最大程度地减少符号间干扰,以减少与数据有关的抖动。对于25Gbps差分高速信令,它显示出差分回波损耗改善了3.1 dB以上,差分插入损耗改善了0.7 dB以上,这意味着端到端眼高增加了17%以上,抖动减少了7%以上在刀片服务器上进行全通道模拟。

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