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首页> 外文会议>2014 Joint IEEE International Symposium on the Applications of Ferroelectrics, International Workshop on Acoustic Transduction Materials and Devices amp; Workshop on Piezoresponse Force Microscopy >Study on the board-level drop test of the stacked memory device by FEA
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Study on the board-level drop test of the stacked memory device by FEA

机译：有限元分析法研究堆叠存储设备的板级跌落测试

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In this study, the drop test simulation for a typical stacked memory device with 8 units integrated vertically on board-level was performed by finite element method. The units were connected with each other through copper lead frames and assembled on the PCB by pins. The computational model of the device was built in ANSYS and the drop test of this board-level assembled device was investigated by numerical method in this study. Using the finite element analysis, the stress in the boardlevel device were predicted under the drop test conditions which is followed the JEDEC standards. In the analysis, appropriate simplification of small structures, e.g. wire bond etc. and the 1/4 model was adopted to overcome the huge computational costs. The results showed the critical locations of the board-level assembled device in the drop test and revealed the most effect parameters. Some suggestions for improving the reliability of POP device were proposed on the basis of the results of computation and analysis.
机译：在这项研究中，通过有限元方法对垂直集成在板上的8个单元的典型堆叠存储设备的跌落测试进行了仿真。这些单元通过铜引线框架相互连接，并通过引脚组装在PCB上。在ANSYS中建立了该器件的计算模型，并通过数值方法对该板级组装器件的跌落测试进行了研究。使用有限元分析，在遵循JEDEC标准的跌落测试条件下，可以预测板级设备中的应力。在分析中，适当简化小结构，例如引线键合等，并且采用1/4模型来克服巨大的计算成本。结果显示了跌落测试中板级组装设备的关键位置，并显示了最有效的参数。在计算分析结果的基础上，提出了一些提高POP设备可靠性的建议。

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