• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>2015 Global Conference on Communication Technologies >Design of high-speed power efficient full adder with body-biasing
【24h】

Design of high-speed power efficient full adder with body-biasing

机译：带有人体偏置的高速节能全加器的设计

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

A new 1-bit full adder cell has been introduced in this paper. According to this approach body-biasing and semi domino logic both are used in a single full adder. Body-biasing technique is used to vary the threshold voltage to operate this adder at higher speed by allowing the faster gate switching. The important thing in this approach is that there is no requirement of any external circuitry for body-biasing. Also, the power consumption of the proposed full adder circuit is very low by using the lower power supply and semi domino logic. Proposed design circuit is 1.5 to 2 times faster than the dynamic gate-level body biased design. The circuit design and analysis are carried out at 45 nm technology in SILVACO-ICCAD environment. The proposed design has lower energy consumption per operation and robust against process and temperature variation.
机译：本文介绍了一种新的1位全加法器单元。根据这种方法，身体偏置和半多米诺逻辑都在单个全加器中使用。体偏置技术用于改变阈值电压，以通过允许更快的栅极开关来使该加法器以更高的速度工作。这种方法的重要之处在于，无需任何外部电路来进行人体偏置。同样，通过使用较低的电源和半多米诺逻辑，提出的全加法器电路的功耗非常低。拟议的设计电路比动态门级主体偏置设计快1.5至2倍。电路设计和分析在SILVACO-ICCAD环境中以45 nm技术进行。所提出的设计具有较低的每次操作能耗，并且能够抵抗工艺和温度变化。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号