Hardware architecture design of face recognition system based on FPGA

机译：基于FPGA的人脸识别系统的硬件架构设计

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A novel hardware architecture for face-recognition system has been proposed in this paper. In order to make the system cost effective a simple yet efficient algorithm of face-recognition system has been used. We have designed, implemented and verified the algorithm in a cyclone III Field Programmable Gate Array (FPGA) chip. Altera DE0 development board which contains a cyclone III chip on it has been used for debugging purpose. We have also ensured for low power consumption such that the chip could be used universally in a wide range of security systems. To develop a simple yet efficient face recognition algorithm (such as PCA, FFT etc.) on digital hardware, we have researched on various face recognition algorithms using MATLAB codes and studied their detection efficiency under various posture and background and also the complexity of the algorithm. To save hardware resource and at the same time to obtain an acceptable level of recognition we have chosen to use Fast Fourier Transform (FFT).

机译：本文提出了一种新颖的人脸识别系统硬件架构。为了使该系统具有成本效益，已经使用了一种简单而有效的面部识别系统算法。我们已经在气旋III现场可编程门阵列（FPGA）芯片中设计，实现和验证了该算法。 Altera DE0开发板上已包含Cyclone III芯片，已用于调试目的。我们还确保了低功耗，使得该芯片可广泛用于各种安全系统中。为了在数字硬件上开发一种简单而有效的人脸识别算法（例如PCA，FFT等），我们使用MATLAB代码研究了各种人脸识别算法，并研究了它们在各种姿势和背景下的检测效率以及该算法的复杂性。为了节省硬件资源并同时获得可接受的识别水平，我们选择使用快速傅里叶变换（FFT）。

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来源
《2015 IEEE International Conference on Innovations in Information , Embedded and Communication Systems》|2015年|1-5|共5页
会议地点 Coimbatore(IN)
作者
Mondol Raktim Kumar; Imran Khan Md.; Mahbubul Hye A.K.; Hassan Asif;
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作者单位

BRAC University, Dhaka, Bangladesh;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
DSP Algorithm; FFT; Face Recognition; Field Programmable Gate Array (FPGA); Image Processing; PCA; VLSI;

机译：DSP算法; FFT;人脸识别;现场可编程门阵列（FPGA）;图像处理; PCA; VLSI;

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机译：嵌入式硬件上的对象识别和姿势估计：FPGA逻辑加速基于SURF的系统设计
2. Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic [J] . Schaeferling Michael, Hornung Ulrich, Kiefer Gundolf International journal of reconfigurable computing . 2012,第6aaPagea1期

机译：嵌入式硬件上的对象识别和姿势估计：FPGA逻辑加速基于SURF的系统设计
3. Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic [J] . MichaelSchaeferling, UlrichHornung, GundolfKiefer International journal of reconfigurable computing . 2012,第6aaPagea1期

机译：嵌入式硬件上的对象识别和姿势估计：FPGA逻辑加速基于SURF的系统设计
4. Hardware architecture design of face recognition system based on FPGA [C] . Mondol Raktim Kumar, Imran Khan Md., Mahbubul Hye A.K., IEEE International Conference on Innovations in Information , Embedded and Communication Systems . 2015

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Hardware architecture design of face recognition system based on FPGA

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