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首页> 外文会议>2016 5th International Conference on Informatics, Electronics and Vision >Design of parity preserving reversible sequential circuits
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Design of parity preserving reversible sequential circuits

机译：奇偶校验可逆时序电路的设计

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Irreversible computing requires consumption of energy to obtain missing bits due to overlapped mapping between input and output vectors. For this reason, reversible computing has become one of the most significant computing processes for the forthcoming computing technology as they dissipate very low power. Therefore, a major research objective in this field is the synthesis of different types of reversible latches and flip flops. A parity preserving reversible new gate is proposed in this paper. A modification of existing Peres gate is also proposed. Using the proposed gates, the conventional flip flops - RS flip flop, JK flip flop, D flip flop and T flip flop are designed. Therefore, the proposed designs are fault tolerant. The master-slave JK flip flop and master-slave D flip flop are also designed using the proposed gates. The proposed circuit designs are superior to the existing designs in terms of number of gates, garbage outputs and quantum costs.
机译：由于输入和输出矢量之间的映射重叠，不可逆计算需要消耗能量来获取丢失的位。由于这个原因，可逆计算已经成为即将到来的计算技术的最重要的计算过程之一，因为它们消耗的功率非常低。因此，该领域的主要研究目标是合成不同类型的可逆锁存器和触发器。本文提出了一种保持奇偶性的可逆新门。还提出了对现有Peres门的修改。使用所提出的门，设计了常规触发器-RS触发器，JK触发器，D触发器和T触发器。因此，所提出的设计是容错的。主从JK触发器和主从D触发器也是使用建议的门设计的。拟议的电路设计在门数，垃圾输出和量子成本方面优于现有设计。

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