Performance evaluation and read stability enhancement of SRAM bit-cell in 16nm CMOS

机译：16nm CMOS中SRAM位单元的性能评估和读取稳定性增强

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Read stability is one of the most important factors for designing efficient SRAM cell. This research presents in-depth understanding of 6T-SRAM cell's functionality and comparative performance study of the bit-cell under three different technology nodes of 32nm, 22nm and 16nm. Measures are taken to mitigate the effect of drastic reduction in Read-Static-Noise-Margin at 16nm CMOS technology by implementing the 8T-SRAM structure. To design a SRAM cell, in the present research, read and hold stability are taken into consideration. Then static noise margins are estimated for hold and read operations by meticulously selecting the cell-parameters. The cell ratio has highly impacted on the operation of the memory cell. Temperature dependence is also analyzed for 6T and 8T cell at 16nm technology. HSPICE simulation software is employed and a set of transistors incorporating high-k/metal gate from PTM high performance models are used in this research.

机译：读取稳定性是设计高效SRAM单元的最重要因素之一。这项研究提供了对6T-SRAM单元功能的深入了解，以及在32nm，22nm和16nm三种不同技术节点下对位单元的比较性能研究。通过实施8T-SRAM结构，采取了一些措施来减轻16nm CMOS技术上的静态静噪裕度大幅降低的影响。为了设计SRAM单元，在本研究中，考虑了读取和保持稳定性。然后，通过精心选择单元参数来估算保持和读取操作的静态噪声容限。单元比率对存储单元的操作有很大影响。还对16nm技术下的6T和8T电池的温度依赖性进行了分析。本研究使用HSPICE仿真软件，并使用了一组结合了PTM高性能模型中的高k /金属栅极的晶体管。

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来源
《2016 5th International Conference on Informatics, Electronics and Vision》|2016年|713-718|共6页
会议地点 Dhaka(BD)
作者
Md Imranur Rahman; Tasnim Bashar; Satyen Biswas;
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作者单位

Department of Electrical and Electronic Engineering, Ahsanullah University of Science and Technology, Dhaka, Bangladesh;

Department of Electrical and Electronic Engineering, Ahsanullah University of Science and Technology, Dhaka, Bangladesh;

Department of Electrical and Electronic Engineering, Ahsanullah University of Science and Technology, Dhaka, Bangladesh;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Capacitance; Transistors; Power demand; SRAM cells; Stability analysis; Thermal stability;

机译：电容;晶体管;功率需求; SRAM单元;稳定性分析;热稳定性;

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专利

1. Differential-read symmetrical 8T SRAM bit-cell with enhanced data stability [J] . Electronics Letters . 2010,第18期

机译：差分读取对称8T SRAM位单元，具有增强的数据稳定性
2. A proposed eleven-transistor (11-T) CMOS SRAM cell for improved read stability and reduced read power consumption [J] . AJAY KUMAR SINGH, MAH MENG SEONG, C. M. R. PRABHU WSEAS Transactions on Circuits and Systems . 2013,第10a12期

机译：拟议的十一晶体管（11-T）CMOS SRAM单元可提高读取稳定性并降低读取功耗
3. DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM [J] . Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Journal of Low Power Electronics . 2010,第3期

机译：纳米CMOS SRAM中基于DOE-ILP的同时功率和读取稳定性优化
4. Performance evaluation and read stability enhancement of SRAM bit-cell in 16nm CMOS [C] . Md Imranur Rahman, Tasnim Bashar, Satyen Biswas International Conference on Informatics, Electronics and Vision . 2016

机译：16NM CMOS中SRAM位细胞的性能评估和读取稳定性增强
5. Design and Performance Evaluation of 8T SRAM Cell Using FinFET and CMOS at 16nm Technology [D] . Mandadi, Prasanth. 2021

机译：在16NM技术中使用FinFET和CMOS的8T SRAM单元的设计与性能评估
6. A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process [O] . Meng-Yin Hsu, Chu-Feng Liao, Yi-Hong Shih, 2017

机译：采用纯CMOS逻辑工艺的具有自抑制电阻切换负载的RRAM集成4T SRAM
7. An Analysis of Power and Stability in 6T, NC, Asymmetric, PP, and P3SRAM Bit-Cells Topologies in 45nm CMOS Technology [O] . Madhurima Kumar, Anshul Arora, Ritu Arora, 2012

机译：45nm CMOS技术中6T，NC，不对称，PP和P3SRAM位拓扑中的功率和稳定性分析

Performance evaluation and read stability enhancement of SRAM bit-cell in 16nm CMOS

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