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Dynamic Characterization of 650 V GaN HEMT with Low Inductance Vertical Phase Leg Design for High Frequency High Power Applications

机译:具有低电感垂直相臂设计的650 V GaN HEMT的动态特性,适用于高频大功率应用

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摘要

In this paper, dynamic characterization of the new 650 V GaN devices from GaN Systems is discussed in detail. The gate driver design from GaN Systems’ application note is also examined. Due to the high slew rate of these devices, it is important to incorporate galvanic isolation between gate driver input and output stage as recommended in [1]. Furthermore, the gate loop and power loop stray inductances and capacitances need to be minimized to curtail the switching noise. To achieve this, vertical power loop design with very small parasitic inductance is proposed. The dynamic characterization carried with this design shows reduction of voltage overshoot to less than half compared to the lateral power loop design from [1]. Finally, the issue of performance degradation of devices with time is also discussed.
机译:在本文中,详细讨论了GaN Systems新型650 V GaN器件的动态特性。还检查了GaN Systems应用笔记中的栅极驱动器设计。由于这些器件的高压摆率,按照[1]中的建议,在栅极驱动器输入和输出级之间加入电流隔离非常重要。此外,栅极回路和电源回路的杂散电感和电容需要最小化以减少开关噪声。为了实现这一点,提出了具有非常小的寄生电感的垂直功率环路设计。与[1]中的横向功率环路设计相比,这种设计所具有的动态特性显示电压过冲降低到不到一半。最后,还讨论了设备性能随时间下降的问题。

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