Design of a VCO-based ADC in 28 nm CMOS

机译：28 nm CMOS中基于VCO的ADC的设计

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A VCO-based ADC is designed and synthesized in a 28 nm FDSOI CMOS process to investigate the scaling benefits of all-digital analog-to-digital conversion. A coarse-fine quantizer is used to obtain high energy efficiency. Common patterns of sample errors at the multi-phase VCO output are identified and mitigated. Final design indicates an ENOB of 13.4 and a Walden FoM of 4.3 fJ/step over a 5 MHz bandwidth while sampling at 150 MHz, according to schematic simulation of the synthesized netlist.

机译：基于VCO的ADC是在28 nm FDSOI CMOS工艺中设计和合成的，旨在研究全数字模数转换的定标效益。粗细量化器用于获得高能效。识别并缓解了多相VCO输出处常见的样本错误模式。根据综合网表的示意性仿真，最终设计表明在5 MHz带宽上的ENOB为13.4，Walden FoM为4.3 fJ / step，同时在150 MHz采样。

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来源
《2016 IEEE Nordic Circuits and Systems Conference》|2016年|1-4|共4页
会议地点 Copenhagen(DK)
作者
Vishnu Unnikrishnan; Mark Vesterbacka;
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作者单位

Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University, Linköping, Sweden 581 83;

Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University, Linköping, Sweden 581 83;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Radiation detectors; Phase measurement; Registers; Voltage-controlled oscillators; Bandwidth; Hardware; Silicon-on-insulator;

机译：辐射探测器;相位测量;寄存器;压控振荡器;带宽;硬件;绝缘体上硅;

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1. A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS [J] . Zhong Yi, Li Shaolan, Tang Xiyuan, IEEE Journal of Solid-State Circuits . 2020,第2期

机译：基于二阶VCO的CTΔΣADC，在40-NM CMOS中使用改进的DPLL结构
2. A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS [J] . Xing Xinpeng, Gielen Georges G. E. Solid-State Circuits, IEEE Journal of . 2015,第3期

机译：在40 nm CMOS中的42 fJ / Step-FoM两步基于VCO的Delta-Sigma ADC
3. A low-power time-domain VCO-based ADC in 65 nm CMOS [J] . Wang Chenluan, Diao Shengxi, Lin Fujiang Journal of Semiconductors . 2014,第10期

机译：65 nm CMOS的低功耗时域基于VCO的ADC
4. Design of a VCO-based ADC in 28 nm CMOS [C] . Vishnu Unnikrishnan, Mark Vesterbacka IEEE Nordic Circuits and Systems Conference . 2016

机译：基于VCO的ADC在28 nm CMOS中设计
5. Time-Based, Low-Power, Low-Offset 5-Bit 1 Gs/S Flash ADC Design in 65nm CMOS Technology [D] . Nasrollahpour, Mehdi 2017

机译：采用65nm CMOS技术的基于时间的低功耗，低失调5位1 Gs / S闪存ADC设计
6. Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process [O] . Ruibo Chen, Hongxia Liu, Wenqiang Song, 2020

机译：具有嵌入式PMOSFET的鲁棒和锁定的免疫LVTSCR器件用于28 nm CMOS过程中的ESD保护
7. A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $DeltaSigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $mu$m CMOS [O] . Matthew Park, Michael H. Perrott 2009

机译：A 78 DB SNDR 87 MW 20 MHz带宽连续时间$ Delta Sigma $ ADC与基于VCO的Integrator和量化器以0.13 $ mu $ M CMOS实现

Design of a VCO-based ADC in 28 nm CMOS

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