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The REPLICA on-chip network

机译:REPLICA片上网络

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摘要

General purpose chip multiprocessors (CMP) are challenging to on-chip intercommunication network designers since one would need low latency, high bandwidth independently of the communication patterns, support for cost-efficient synchronization, and low energy consumption to support arbitrary applications. Currently popular ring-based networks provide straight-forward design, far superior performance than bus-based alternatives and extensibility over crossbars. As the number of processors cores increases, however, the effective bandwidth between most parts of a ring remains constant implying higher capacity solutions are needed to support scaled-up CMPs. In this paper we describe the on-chip network of our REPLICA CMP. It is based on an acyclic bandwidth-scaled multi-mesh topology and uses routing with elastic synchronization mechanism. To avoid congestion and hot spots in shared memory access traffic can be randomized with a programmable hashing function. The performance of the network is evaluated preliminarily on our experimental 4-core and 16-core REPLICA FPGA implementations and REPLICA simulator.
机译:通用芯片多处理器(CMP)对片上互通网络设计人员提出了挑战,因为一个人需要低延迟,独立于通信模式的高带宽,支持具有成本效益的同步以及低能耗来支持任意应用。当前流行的基于环的网络提供了直接的设计,其性能远远优于基于总线的替代产品,并且具有可扩展性。但是,随着处理器内核数量的增加,环的大部分之间的有效带宽保持恒定,这意味着需要更高容量的解决方案来支持按比例放大的CMP。在本文中,我们描述了REPLICA CMP的片上网络。它基于非循环带宽缩放的多网状拓扑,并使用具有弹性同步机制的路由。为避免共享内存中的拥塞和热点,可以使用可编程哈希函数将访问流量随机化。预先在我们的实验性4核和16核REPLICA FPGA实现和REPLICA仿真器上评估了网络的性能。

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