首页> 外文会议>2016 IEEE Nordic Circuits and Systems Conference >Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aids
【24h】

Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aids

机译:180纳米CMOS中的无电容,低压差线性稳压器,用于助听器

获取原文
获取原文并翻译 | 示例

摘要

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a new dual loop topology. The regulator utilizes the feedback loops to satisfy the challenges for hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of an off-chip discrete capacitor connected at the output and operates with 0-100 pF capacitive load. The design has been implemented in a 0.18 μm CMOS process. The proposed regulator has a low component count and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from 1.0 V-1.4 V supply. A current step load from 250-500 μA with an edge time (rise and fall time) of 1 ns results at ΔVOut of 64 mV with a settling time of 3 μs when CL =0. The power supply rejection ratio (PSRR) at 1 kHz is 63 dB.
机译:本文提出了一种基于新型双环路拓扑的无电容器低压降(LDO)线性稳压器。调节器利用反馈回路来满足助听器设备的挑战,其中包括快速的瞬态性能和在负载电流快速变化下的小电压尖峰。提出的设计无需在输出端连接片外分立电容器即可工作,并且可在0-100 pF的电容负载下工作。该设计已通过0.18μmCMOS工艺实现。拟议的稳压器组件数量少,适用于片上系统集成。它通过1.0 V至1.4 V电源将输出电压调节为0.9V。当CL = 0时,在ΔVOut为64 mV且建立时间为3μs的情况下,从250-500μA的电流阶跃负载开始,边沿时间(上升和下降时间)为1 ns。 1 kHz时的电源抑制比(PSRR)为63 dB。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号