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首页> 外文会议>2016 IEEE Nordic Circuits and Systems Conference >Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing
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Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing

机译：28 nm FDSOI中的超低压加法器探索多偏置技术，以实现器件尺寸确定

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摘要

Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, functional yield of CMOS logic gates in the subthreshold region. In this work, the PMOS/NMOS strength ratio was balanced using a poly-biasing technique in conjunction with back-gate biasing provided in a 28 nm fully depleted silicon on insulator (FDSOI) technology. A 32-bit adder based on minority-3 (min-3) gates and a 16-bit adder based on Boolean gates have been implemented. Chip measurement results show highly energy efficient adders, so that the 32-bit and 16-bit adders achieved minimum energy point (MEP) of 21.5 fJ at 300 mV and 12.62 fJ at 250 mV, respectively. In comparison to adders reported in other works in the same technology, the energy per 1-bit addition of the 32-bit adder is improved by 35% and for the 16-bit adder this improvement in energy consumption is 23%. The designed adders were functional down to a supply voltage of 110 mV. Additionally, the minimum Vdd of the 32-bit adder decreased to 79 mV by applying a reverse back bias voltage to the PMOS devices.
机译：平衡PMOS / NMOS强度比是最大程度提高噪声容限，从而提高亚阈值区域内CMOS逻辑门功能产量的关键问题。在这项工作中，PMOS / NMOS强度比使用多偏置技术与28 nm完全耗尽绝缘体上硅（FDSOI）技术中提供的背栅偏置相平衡。已经实现了基于少数民族3（min-3）门的32位加法器和基于布尔门的16位加法器。芯片测量结果显示出高能效加法器，因此32位和16位加法器在300 mV时的最小能量点（MEP）分别为21.5 fJ和250 mV时的12.62 fJ。与采用相同技术的其他作品中报道的加法器相比，32位加法器每1位加法的能耗提高了35％，而对于16位加法器，此能耗降低了23％。设计的加法器可在低至110 mV的电源电压下正常工作。此外，通过向PMOS器件施加反向反向偏置电压，该32位加法器的最小Vdd降至79 mV。

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  • 来源
  • 会议地点 Copenhagen(DK)
  • 作者

    Ali Asghar Vatanjou; Even Late; Trond Ytterdal; Snorre Aunet;

  • 作者单位

    Department of Electronics and Telecommunications, Norwegian University of Science and Technology, O. S. Bragstads Plass 2 A, 7491 Trondheim, Norway;

    Department of Electronics and Telecommunications, Norwegian University of Science and Technology, O. S. Bragstads Plass 2 A, 7491 Trondheim, Norway;

    Department of Electronics and Telecommunications, Norwegian University of Science and Technology, O. S. Bragstads Plass 2 A, 7491 Trondheim, Norway;

    Department of Electronics and Telecommunications, Norwegian University of Science and Technology, O. S. Bragstads Plass 2 A, 7491 Trondheim, Norway;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Adders; Logic gates; Delays; MOSFET; Silicon-on-insulator; Energy measurement;

    机译：加法器;逻辑门;延迟; MOSFET;绝缘体上硅;能量测量;

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