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Performance analysis of seven level three phase asymmetric multilevel Inverter at various modulation indices

机译:七电平三相不对称多电平逆变器在各种调制指标下的性能分析

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This paper analyses the performance of an asymmetric topology of three phase seven level Multi-Level Inverter (MLI) at various modulation indices. The ultimate aim of carrying out the analysis is to vary the modulation index so as to obtain an optimum value at minimum Total Harmonic Distortion (THD). This topology offers a major advantage such that it contains lower number of switches and input DC source as compared to the conventional and other existing three phase MLI topologies. Amongst the conventional topologies such as Diode Clamp Multi-Level Inverter (DCMLI), Flying Capacitor Multi-Level Inverter (FCMLI) and Cascaded Multi-Level Inverter (CMLI), CMLI requires minimum number of components as we go for higher number of levels. In case of seven level, three phase MLI's, conventional CMLI requires thirty six switches whereas in the proposed topology, the required number of switches are one third of the conventional CMLI i.e. only twelve switches are required for the generation of three phase seven level output voltage. For achieving this, Multi-carrier Sinusoidal Pulse Width Modulation (MSPWM) technique is used. The topology is successfully simulated and verified using Simu-link tool at various modulation indices and detailed comparison between modulation indices and THD thus obtained is also carried out.
机译:本文分析了三相七电平多电平逆变器(MLI)在各种调制指标下的不对称拓扑的性能。进行分析的最终目的是改变调制指数,以便以最小的总谐波失真(THD)获得最佳值。与传统的和其他现有的三相MLI拓扑相比,此拓扑提供了一个主要优势,即它包含的开关和输入DC源数量更少。在诸如二极管钳位多电平逆变器(DCMLI),飞跨电容器多电平逆变器(FCMLI)和级联多电平逆变器(CMLI)之类的常规拓扑中,随着我们追求更高的级别数,CMLI需要的组件数量最少。在七电平三相MLI的情况下,常规CMLI需要三十六个开关,而在建议的拓扑中,所需的开关数量是常规CMLI的三分之一,即,仅需要十二个开关即可生成三相七电平输出电压。为了实现这一点,使用了多载波正弦脉冲宽度调制(MSPWM)技术。使用Simu-link工具在各种调制指数下成功地对拓扑进行了仿真和验证,并对调制指数与THD进行了详细的比较。

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