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首页> 外文会议>2016 World Conference on Futuristic Trends in Research and Innovation for Social Welfare >Design and comparative analysis of binary and quaternary logic circuits
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Design and comparative analysis of binary and quaternary logic circuits

机译：二元和四元逻辑电路的设计与比较分析

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The project presents the design of high performance quaternary Combinational circuits for lower power dissipation. Most of the digital electronic systems are based on the binary logic design which is limited by the requirement of interconnections which increases the chip area. The solution to this problem can be achieved using multi valued logic (MVL)/Quaternary logic. Most of the authors used methods which required Quaternary to Binary and Binary to Quaternary conversion for any arithmetic and logic operation and achieved satisfactory performances. Our aim is to develop MVL/Quaternary logic for combinational circuits under case study without converting these levels into binary logic and vice-versa. It will reduce one additional step, and improve the performance offering less chip size, saving more power. The design is targeted for 0.18um CMOS technology and the design tool for simulation will be Advanced Design System tool (ADS).
机译：该项目提出了用于降低功耗的高性能四元组合电路的设计。大多数数字电子系统都基于二进制逻辑设计，该二进制逻辑设计受到互连需求的限制，互连会增加芯片面积。可以使用多值逻辑（MVL）/四元逻辑来解决此问题。大多数作者使用的方法需要对任何算术和逻辑运算进行四元到二进制和二元到四元的转换，并获得令人满意的性能。我们的目标是在案例研究中为组合电路开发MVL /四元逻辑，而无需将这些电平转换为二进制逻辑，反之亦然。它将减少一个额外的步骤，并通过减小芯片尺寸，节省更多功率来提高性能。该设计针对0.18um CMOS技术，而用于仿真的设计工具将是Advanced Design System工具（ADS）。

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