Deterministic methodology to evaluate BTI impact on logic gates propagation delay

机译：评估BTI对逻辑门传播延迟的影响的确定性方法

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The propagation delay variation induced by BTI in logic gates is studied. Using the deterministic BTI model introduced by our group in [1], a detailed description of its implementation in a commercial SPICE tool is presented. Simulations concerning the dependence of the BTI-induced propagation delay on the supply voltage and on the DC stress time of NAND gates are presented. The different impact of BTI for both low-high-low and high-low-high levels pulses is evaluated.

机译：研究了BTI在逻辑门中引起的传输延迟变化。使用我们小组在[1]中介绍的确定性BTI模型，详细介绍了其在商用SPICE工具中的实现。提出了有关BTI引起的传播延迟对电源电压和与非门的DC应力时间的依赖性的仿真。评估了BTI对低-高-低和高-低-高电平脉冲的不同影响。

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来源
《2017 32nd Symposium on Microelectronics Technology and Devices》|2017年|1-4|共4页
会议地点 Fortaleza(BR)
作者
Gabriela F. Furtado; Thiago H. Both; Gilson I. Wirth;
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作者单位

Microelectronics Program (PGMICRO), Federal University of Rio Grande do Sul. Porto Alegre, Brazil;

Microelectronics Program (PGMICRO), Federal University of Rio Grande do Sul. Porto Alegre, Brazil;

Microelectronics Program (PGMICRO), Federal University of Rio Grande do Sul. Porto Alegre, Brazil;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Propagation delay; Stress; MOSFET; Logic gates; Threshold voltage; Delays;

机译：传播延迟;应力; MOSFET;逻辑门;阈值电压;延迟;;

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专利

1. Analysis and modelling of initial delay time and its impact on propagation delay of CMOS logic gates [J] . Yang Y.-H., Wu C.-Y. IEE Proceedings. Part G, Electronic Circuits and Systems . 1989,第5期

机译：初始延迟时间的分析和建模及其对CMOS逻辑门的传播延迟的影响
2. Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model [J] . Halil Kuekner, Pieter Weckx, Praveen Raghavan, Microprocessors and microsystems . 2013,第8ptaA期

机译：基于基于原子阱的BTI模型，占空比，应力刺激，栅极和驱动强度对栅极延迟退化的影响
3. The effect of signal activity on propagation delay of CMOS logic gates driving coupled on-chip interconnections [J] . Kevin T. Tang, Eby G. Friedman Analog Integrated Circuits and Signal Processing . 2002,第3期

机译：信号活动对驱动耦合的片上互连的CMOS逻辑门的传播延迟的影响
4. Deterministic methodology to evaluate BTI impact on logic gates propagation delay [C] . Gabriela F. Furtado, Thiago H. Both, Gilson I. Wirth Symposium on Microelectronics Technology and Devices . 2017

机译：确定性方法评估BTI对逻辑栅极传播延迟的影响
5. Methodology for Analysis, Modeling and Simulation of Airport Gate-waiting Delays [D] . Wang, Jianfeng 2011

机译：机场登机口等候延误的分析，建模和仿真方法
6. Signal Propagation and Logic Gating in Networks of Integrate-and-Fire Neurons [O] . Tim P. Vogels, L. F. Abbott 2005

机译：集成火神经元网络中的信号传播和逻辑门控
7. Optimization of SFQ Logic Gate Considering Dependence of its Signal Propagation Delay on the Bias Voltage [O] . Otsubo Mikio, Yamanashi Yuki, Yoshikawa Nobuyuki 2014

机译：考虑信号传播延迟与偏置电压相关性的SFQ逻辑门的优化

Deterministic methodology to evaluate BTI impact on logic gates propagation delay

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