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Design and analysis of high performance pulse ring VCO

机译:高性能脉冲环压控振荡器的设计与分析

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This paper presents a low phase noise, low power, wide tuning range, small area pulse ring oscillator fabricated in inexpensive 130nm CMOS technology. The ring uses very non-linear Pulse gates instead of conventional inverters as buffers substantially reducing the impulse sensitivity function (ISF) and thus the phase noise. The timing signal is rising-edge and ground referenced, allowing the supply to be used as control voltage. 6dB phase noise improvement is projected in ISF based phase noise simulation over a same frequency ring oscillator. Fabricated ring oscillators show a phase noise of -97.46 dBC/Hz at 1MHz offset for 1.889GHz oscillator at 2.94mW power consumption and -95.13 dBC/Hz at 1MHz offset for 897MHz oscillator at 617uW power consumption. The oscillators have a tuning range of 513MHz to 2.64GHz. Figure of merit of the design shows a better performance than any other non phase locked voltage controlled ring oscillator.
机译:本文提出了一种以廉价的130nm CMOS技术制造的低相位噪声,低功耗,宽调谐范围,小面积脉冲环形振荡器。该环使用非常非线性的脉冲门代替传统的反相器作为缓冲器,从而大大降低了脉冲灵敏度功能(ISF),从而降低了相位噪声。时序信号为上升沿,并以地为参考,允许电源用作控制电压。在相同频率的环形振荡器上,基于ISF的相位噪声仿真预计可提高6dB的相位噪声。预制环形振荡器在2.94mW功耗下对于1.889GHz振荡器在1MHz偏移处显示出-97.46 dBC / Hz的相位噪声,在617uW功耗下对于897MHz振荡器在1MHz偏移处显示-95.13 dBC / Hz。振荡器的调谐范围为513MHz至2.64GHz。该设计的品质因数显示出比任何其他非锁相压控环形振荡器都更好的性能。

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