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首页> 外文会议>2017 IEEE Nordic Circuits and Systems Conference: NORCHIP and International Symposium of System-on-Chip >Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology
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Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology

机译：探索22nm FDSOI技术中紧密耦合加速器的FPGA架构

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摘要

Reconfigurable microprocessors extend the concept of application specific instruction set processors (ASIPs) to allow customization at runtime. Previous research mainly focused on exploiting this feature in high-level applications, without regard to the design and architecture of the reconfigurable hardware. In contrast, this paper explores the design space for tight coupled, fine-grained accelerators with a detailed physical model. We performed a comprehensive exploration of architectures for generic island-style field programmable gate arrays (FPGAs) with a custom benchmark set, a flexible toolchain, and a commercial 22nm FDSOI technology. To annotate FPGA architectures with plausible estimates for area and delay, we improved existing physical models with a customized area model. Multiple layouts validate the accuracy of this model and show that assumptions of prevailing area models do not capture layout restrictions of advanced technology nodes. Results indicate an almost constant area delay product for lookup tables (LUTs) with three to five inputs. Clusters with few logic elements or small LUTs appear to be less efficient than previously thought.
机译：可重新配置的微处理器扩展了专用指令集处理器（ASIP）的概念，以允许在运行时进行自定义。先前的研究主要集中在高级应用程序中利用此功能，而不考虑可重新配置硬件的设计和体系结构。相反，本文探索了具有详细物理模型的紧密耦合，细粒度加速器的设计空间。我们对通用岛式现场可编程门阵列（FPGA）的架构进行了全面的探索，该架构具有自定义基准测试集，灵活的工具链和商用22nm FDSOI技术。为了用合理的面积和延迟估计来注释FPGA体系结构，我们使用定制的面积模型改进了现有的物理模型。多种布局验证了此模型的准确性，并表明主流区域模型的假设未捕获先进技术节点的布局限制。结果表明具有三到五个输入的查找表（LUT）的面积延迟积几乎恒定。逻辑元素很少或LUT较小的集群似乎效率不高。

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