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首页> 外文会议>2017 IEEE Nordic Circuits and Systems Conference: NORCHIP and International Symposium of System-on-Chip >Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays
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Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays

机译：设计差分3R-2bit RRAM单元以增强交叉点RRAM阵列中的读取余量

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摘要

Conventional memories face serious design challenges as process feature size of transistor shrinks to ultra-low sizes, hence the need for having an alternative for conventional memory technologies is inevitable. The cross-point architectures of resistive random access memories (RRAM) have been introduced as a cost-competitive and high bit-density candidate to replace flash memories. However, deficiencies like sneak leakage current has been a major barrier to reach this goal by reducing the read margin and increasing the power consumption. In order to tackle the mentioned drawbacks in the cross-point architectures, various approaches like differential 2R-1bit and complementary RRAM cells have been proposed, but these solutions have either degraded the density or increased the delay of the read operation. In this paper, in order to make a better trade-off between density, read margin, and power consumption, a 3R-2bit cross-point architecture has been proposed that stores two-bit data in three resistive RRAM elements. In addition, a sense-before-write technique has been applied to maintain endurance and power consumption by preventing excessive write operation. To show advantages of the proposed scheme during the read operation, the simple and the differential 2R-1bit cross-point architectures have been compared with the 3R-2bit architecture of the same bit size under different array sizes. The results show significant improvement in read margin as well as saving up to 90% in static power consumption compared to the differential 2R-1bit scheme.
机译：由于晶体管的工艺特征尺寸缩小到超低尺寸，常规存储器面临严重的设计挑战，因此不可避免地需要替代常规存储器技术。电阻随机存取存储器（RRAM）的交叉点架构已被引入，以取代闪存成为具有成本竞争力的高位密度候选者。但是，诸如漏电漏电流之类的缺陷已成为通过减少读取余量和增加功耗来实现此目标的主要障碍。为了解决交叉点架构中提到的缺点，已经提出了各种方法，例如差分2R-1bit和互补RRAM单元，但是这些解决方案要么降低了密度，要么增加了读取操作的延迟。在本文中，为了在密度，读取余量和功耗之间取得更好的平衡，已经提出了一种3R-2位交叉点架构，该架构将两位数据存储在三个电阻RRAM元件中。另外，已经采用写前感测技术来通过防止过度的写操作来维持耐久性和功耗。为了在读取操作期间显示所提出方案的优点，已将简单和差分2R-1bit交叉点架构与相同位大小，不同阵列大小的3R-2bit架构进行了比较。结果表明，与差分2R-1bit方案相比，读取余量显着提高，并节省了高达90％的静态功耗。

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