• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques >A low-area based costas loop implementation for BPSK signals
【24h】

A low-area based costas loop implementation for BPSK signals

机译：基于低区域的BPSK信号的costas循环实现

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Modulation and Demodulation are the most critical blocks in a communication system. Demodulators used in coherent communication receivers not only get back the message signal, but also perform phase error detection and correction. Phase error detection and correction involves tuning or adjusting the phase of the reference signal to that of the carrier signal received. This is an iterative process. One of the popular techniques employed for phase error detection and correction is the Costas Loop. There has been research about Numerically Controlled Oscillators (NCO) based on CORDIC algorithm being used in a Costas Loop [1]. The other simple yet memory expensive alternative to the CORDIC algorithm is to use a LookUp Table (LUT) based technique. This paper tries to model a Costas Loop based on each of the methods separately and then compare the results. There has been notable work involving the use of symmetric FIR filters in a Costas Loop [2] which saves on memory. However there has been no attempt to compare the results of folded filter (uses one half of the filter coefficients only) architecture versus that obtained from unfolded filter (uses the entire coefficient sequence) architecture implementations. This paper compares the results obtained from folded filter implementation versus that obtained from unfolded filter implementation. The system was simulated using MATLAB and Simulink. The Verilog implementation was programmed on Spartan 3e FPGA board.
机译：调制和解调是通信系统中最关键的模块。相干通信接收机中使用的解调器不仅返回消息信号，而且还执行相位误差检测和校正。相位误差检测和校正涉及将参考信号的相位调整或调整为接收到的载波信号的相位。这是一个反复的过程。用于相位误差检测和校正的流行技术之一是Costas Loop。已经有关于基于CORDIC算法的数控振荡器（NCO）在Costas回路中的研究[1]。 CORDIC算法的另一种简单但内存昂贵的替代方法是使用基于查找表（LUT）的技术。本文尝试分别基于每种方法对Costas Loop进行建模，然后比较结果。值得注意的工作涉及在节省内存的Costas Loop [2]中使用对称FIR滤波器。然而，没有尝试将折叠滤波器（仅使用滤波器系数的一半）架构的结果与从展开滤波器（使用整个系数序列）架构实现的结果进行比较。本文将折叠式滤波器实现与非折叠式滤波器实现的结果进行了比较。使用MATLAB和Simulink对系统进行了仿真。 Verilog实现在Spartan 3e FPGA板上编程。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号