Implementation of 5–32 address decoders for SRAM memory in 180nm technology

机译：以180nm技术实现用于SRAM存储器的5–32地址解码器

获取原文

获取原文并翻译 | 示例

页面导航

摘要
著录项
相似文献
相关主题

摘要

SRAM memories are very important building blocks of most of the digital applications like microprocessors and different levels of cache memories [8], of which Address decoders are the significant components. They play a crucial part in decoding the addresses. These decoders will decide the capacity of memory cells as well as efficiency of read operations. Hence the performance of SRAM memory also depend upon these address decoders. This paper studies the already existing type of decoders for SRAM memory. Traditional address decoders consume almost 50% of the total power and time of memory chip. An efficient and modified address decoding topology is implemented which counts the least number of transistors in order to reduce the range of SRAM using only one 2-4 decoder, 3-8 decoder and row decoders in CMOS 180nm technology using cadence virtuoso tool, and is compared with different types of decoders.

机译：SRAM存储器是大多数数字应用（例如微处理器）和不同级别的高速缓存[8]的重要组成部分，其中地址解码器是重要的组成部分。它们在解码地址中起着至关重要的作用。这些解码器将决定存储单元的容量以及读取操作的效率。因此，SRAM存储器的性能也取决于这些地址解码器。本文研究了用于SRAM存储器的解码器的现有类型。传统的地址解码器几乎消耗了存储芯片总功耗和时间的50％。实现了一种高效且经过修改的地址解码拓扑，该拓扑计算了最少数量的晶体管，以使用cadence virtuoso工具仅使用CMOS 180nm技术中的一个2-4解码器，3-8解码器和行解码器来减少SRAM的范围，并且与不同类型的解码器进行比较。

著录项

来源
《2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques》|2017年|110-114|共5页
会议地点 Mysuru(IN)
作者
B N Bagamma; K S Vasundara Patel; Prasad Ravi;
展开▼
作者单位

Department of ECE, BMS College of Engineering, Bangalore, India (Affiliated to VTU, Belagavi);

Department of ECE, BMS College of Engineering, Bangalore, India (Affiliated to VTU, Belagavi);

Intel Technology, pvt, Ltd, Bangalore, India;

展开▼
会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Decoding; Random access memory; Delays; Logic gates; Transistors; Power demand; Memory management;

机译：解码;随机存取存储器;延迟;逻辑门;晶体管;功率需求;存储器管理;;

相似文献

外文文献
中文文献
专利

1. Design of low power and high read stability 8T-SRAM memory based on the modified Gate Diffusion Input (m-GDI) in 32 nm CNTFET technology [J] . Abiri Ebrahim, Darabi Abdolreza Microelectronics journal . 2015,第12PTaA期

机译：基于32 nm CNTFET技术的改进的栅极扩散输入（m-GDI），设计了低功耗，高读取稳定性的8T-SRAM存储器
2. Design of Peripheral Circuits for the Implementation of Memory Array Using Data-Aware (DA) SRAM Cell in 65 nm CMOS Technology for Low Power Consumption [J] . Ajay Kumar Singh, Mohammad-Sadegh Saadatzi, C. Venkataseshaiah Journal of Low Power Electronics . 2016,第1期

机译：用于低功耗的65 nm CMOS技术中使用数据感知（DA）SRAM单元实现存储阵列的外围电路设计
3. DESIGN, IMPLEMENTATION OF LOW-POWER AND HIGH-PERFORMANCE STATIC ADDRESS DECODER STRUCTURES USING 22-nm CMOS TECHNOLOGY [J] . M. Madhusudhan Reddy, M. Sailaja, K. Babulu Far East Journal of Electronics and Communications . 2018,第8期

机译：利用22nm CMOS技术设计，实现低功耗，高性能静态地址解码器结构
4. Implementation of 5–32 address decoders for SRAM memory in 180nm technology [C] . B N Bagamma, K S Vasundara Patel, Prasad Ravi International Conference on Electrical, Electronics, Communication, Computer and Optimization Techniques . 2017

机译：在180nm技术中实现5-32个地址解码器，用于SRAM存储器
5. A 32-word by 32-bit three-port bipolar register file implemented using a silicon germanium HBT BiCMOS technology. [D] . Steidl, Samuel Aloysius. 2001

机译：使用硅锗HBT BiCMOS技术实现的32字乘32位三端口双极性寄存器文件。
6. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology [O] . Sukanta Roy, Harikrishnan Ramiah, Ahmed Wasif Reza, -1

机译：基于180nm CMOS技术的基于MEMS的振荡器设计
7. Design and Implementation of 8K-bits Low Power SRAM in 180nm Technology [O] . Sreerama Reddy G M, P Chandrasekhara Reddy 2009

机译：180nm工艺中8K位低功耗sRam的设计与实现

Implementation of 5–32 address decoders for SRAM memory in 180nm technology

摘要

著录项

相似文献

相关主题

期刊订阅