Implementation of VS-PLL structure on FPGA and performaces evaluation

机译：VS-PLL结构在FPGA上的实现和性能评估

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In this paper method of implementation VS-PLL structure on FPGA circuit is described as well performances of proposed structure are presented. It was pointed out that special attention should be paid to the method of mapping VS-PLL structure from a continuous to a discrete domain, in order to does not volatile given performances. Also, it has been shown that MATLAB with all its tools can be used to perform these complex tasks.

机译：本文介绍了在FPGA电路上实现VS-PLL结构的方法，并给出了所提出结构的性能。有人指出，应特别注意将VS-PLL结构从连续域映射到离散域的方法，以使给定性能不易波动。而且，已经证明MATLAB及其所有工具都可以用来执行这些复杂的任务。

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来源
《2018 17th International Symposium INFOTEH-JAHORINA》|2018年|1-5|共5页
会议地点 East Sarajevo(BA)
作者
Milica Ristovic Krstic; Srdjan Lale; Slobodan Lubura; Milomir Soja;
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作者单位

University of East Sarajevo, Faculty of Electrical Engineering, Vuka Karadzica 30, 7112 East Sarajevo, BiH;

University of East Sarajevo, Faculty of Electrical Engineering, Vuka Karadzica 30, 7112 East Sarajevo, BiH;

University of East Sarajevo, Faculty of Electrical Engineering, Vuka Karadzica 30, 7112 East Sarajevo, BiH;

University of East Sarajevo, Faculty of Electrical Engineering, Vuka Karadzica 30, 7112 East Sarajevo, BiH;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Field programmable gate arrays; Phase locked loops; Matlab; Hardware design languages; Frequency estimation; Mathematical model; Simulation;

机译：现场可编程门阵列;锁相环; Matlab;硬件设计语言;频率估计;数学模型;仿真;;
入库时间 2022-08-26 14:05:04

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Implementation of VS-PLL structure on FPGA and performaces evaluation

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