• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>2018 76th Device Research Conference >An Improved 1T-DRAM Cell Using TiO2as the Source and Drain of an n-Channel PD-SOI MOSFET
【24h】

An Improved 1T-DRAM Cell Using TiO2as the Source and Drain of an n-Channel PD-SOI MOSFET

机译：TiO 2 作为n沟道PD-SOI MOSFET的源漏的改进型1T-DRAM单元

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Due to fabrication challenges for the scaling of the capacitor of a conventional DRAM cell below 100 nm technology node, the concept of 1 T-DRAM cell[I] was proposed as an alternative. In all-Si 1T-DRAM cell, the body of an n-channel PD-SOI MOSFET is used as the storage node. The biggest drawback for all-Si 1 T-DRAM cell is it's low retention time which does not meet the ITRS specification (64 ms at 358 K) [2]. As a solution to this problem, we propose a novel capacitor-less 1 T-DRAM cell, where intrinsically n-type TiOn2n[3] is used as the sourceldrain material and silicon as the channel of an n-channel partially depleted SOI MOSFET. Large valance band offset between TiOn2nand Sin$(Delta E_{V}approx 2 eV)$nis utilized for storing larger number of excess holes in the body for a longer time than is possible with an all-Si 1T-DRAM cell. We report an improvement in retention time as well as sense margin at bothn$T=300 K$nandn$T=358 K$nfor our proposed DRAM cell through well calibrated TCAD simulations [4]. The extracted retention time for the proposed TiOn2nsource/drain 1T-DRAM cell is 3.5 s and 160 ms atn$T=300 K$nand 358n$K$nrespectively and for all-Si 1 T-DRAM cell, it is 1.5 ms andn$150 mu s$natn$T=300 K$nandn$T=358 K$nrespectively.
机译：由于在100 nm技术节点以下缩小传统DRAM单元电容器的制造难度，因此提出了1 T-DRAM单元[I]的概念作为替代方案。在全硅1T-DRAM单元中，n沟道PD-SOI MOSFET的本体用作存储节点。全Si 1 T-DRAM单元的最大缺点是保留时间短，不符合ITRS规范（358 K下为64 ms）[2]。为了解决这个问题，我们提出了一种新型的无电容器1 T-DRAM单元，其中本质上是n型TiOn 2 n [3]用作源漏材料，硅用作n沟道部分耗尽SOI MOSFET的沟道。 TiOn 2之间的价带大偏移 nand Sin $ （ΔE_{V}约2eV）·nis被用于比全Si 1T-DRAM单元更长的时间在体内存储大量多余的空穴。我们在n $ T = 300 K $ nandn $T=358 K $ texn，它通过经过良好校准的TCAD仿真[4]用于我们提出的DRAM单元。拟议的TiOn 2 nsource / drain 1T-DRAM单元在atn $T=300 K $ nand 358n $ K $ n分别对于全Si 1 T-DRAM单元为1.5 ms，n 150美元s $ natn $ T = 300 K $ nandn $ T = 358 K $ 分别。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号