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首页> 外文会议>42th Annual International Symposium on Computer Architecture >Hi-fi playback: Tolerating position errors in shift operations of racetrack memory
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Hi-fi playback: Tolerating position errors in shift operations of racetrack memory

机译：高保真播放：允许在赛道记忆的移位操作中出现位置错误

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摘要

Racetrack memory is an emerging non-volatile memory based on spintronic domain wall technology. It can achieve ultra-high storage density. Also, its read/write speed is comparable to that of SRAM. Due to the tape-like structure of its storage cell, a “shift” operation is introduced to access racetrack memory. Thus, prior research mainly focused on minimizing shift latency/energy of racetrack memory while leveraging its ultra-high storage density. Yet the reliability issue of a shift operation, however, is not well addressed. In fact, racetrack memory suffers from unsuccessful shift due to domain misalignment. Such a problem is called “position error” in this work. It can significantly reduce mean-time-to-failure (MTTF) of racetrack memory to an intolerable level. Even worse, conventional error correction codes (ECCs), which are designed for “bit errors”, cannot protect racetrack memory from the position errors. In this work, we investigate the position error model of a shift operation and categorize position errors into two types: “stop-in-middle” error and “out-of-step” error. To eliminate the stop-in-middle error, we propose a technique called sub-threshold shift (STS) to perform a more reliable shift in two stages. To detect and recover the out-of-step error, a protection mechanism called position error correction code (p-ECC) is proposed. We first describe how to design a p-ECC for different protection strength and analyze corresponding design overhead. Then, we further propose how to reduce area cost of p-ECC by leveraging the “overhead region” in a racetrack memory stripe. With these protection mechanisms, we introduce a position-error-aware shift architecture. Experimental results demonstrate that, after using our techniques, the overall MTTF of racetrack memory is improved from 1.33µs to more than 69 years, with only 0.2% performance degradation. Trade-of- among reliability, area, performance, and energy is also explored with comprehensive discussion.
机译：跑道存储器是一种基于自旋电子域壁技术的新兴非易失性存储器。它可以实现超高存储密度。而且，其读/写速度与SRAM相当。由于其存储单元的带状结构，引入了“移位”操作来访问赛道存储器。因此，先前的研究主要集中在最小化赛道存储器的移位等待时间/能量上，同时利用其超高存储密度。然而，变速操作的可靠性问题并未得到很好的解决。实际上，由于域未对齐，跑道存储器的移位失败。在这项工作中，这样的问题称为“位置错误”。它可以将跑道记忆的平均故障平均时间（MTTF）降低到无法忍受的水平。更糟糕的是，为“位错误”而设计的常规纠错码（ECC）无法保护跑道存储器免受位置错误的影响。在这项工作中，我们研究了换档操作的位置误差模型，并将位置误差分为两种类型：“中间停止”误差和“失步”误差。为了消除中间停止错误，我们提出了一种称为亚阈值移位（STS）的技术，可以在两个阶段中执行更可靠的移位。为了检测和恢复失步误差，提出了一种称为位置误差校正码（p-ECC）的保护机制。我们首先描述如何设计具有不同保护强度的p-ECC并分析相应的设计开销。然后，我们进一步提出了如何通过利用赛道存储条中的“开销区域”来降低p-ECC的面积成本的方法。通过这些保护机制，我们引入了位置错误感知转换架构。实验结果表明，使用我们的技术后，跑道存储器的总体MTTF从1.33µs改善到69年以上，而性能下降仅为0.2％。通过全面讨论，还探讨了可靠性，面积，性能和能量之间的折衷。

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