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首页> 外文会议>42th Annual International Symposium on Computer Architecture >MiSAR: Minimalistic synchronization accelerator with resource overflow management
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MiSAR: Minimalistic synchronization accelerator with resource overflow management

机译：MiSAR：具有资源溢出管理功能的简约同步加速器

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While numerous hardware synchronization mechanisms have been proposed, they either no longer function or suffer great performance loss when their hardware resources are exceeded, or they add significant complexity and cost to handle such resource overflows. Additionally, prior hardware synchronization proposals focus on one type (barrier or lock) of synchronization, so several mechanisms are likely to be needed to support real applications, many of which use locks, barriers, and/or condition variables. This paper proposes MiSAR, a minimalistic synchronization accelerator (MSA) that supports all three commonly used types of synchronization (locks, barriers, and condition variables), and a novel overflow management unit (OMU) that dynamically manages its (very) limited hardware synchronization resources. The OMU allows safe and efficient dynamic transitions between using hardware (MSA) and software synchronization implementations. This allows the MSA's resources to be used only for currently-active synchronization operations, providing significant performance benefits even when the number of synchronization variables used in the program is much larger than the MSA's resources. Because it allows a safe transition between hardware and software synchronization, the OMU also facilitates thread suspend/resume, migration, and other thread-management activities. Finally, the MSA/OMU combination decouples the instruction set support (how the program invokes hardware-supported synchronization) from the actual implementation of the accelerator, allowing different accelerators (or even wholesale removal of the accelerator) in the future without changes to OMU-compatible application or system code. We show that, even with only 2 MSA entries in each tile, the MSA/OMU combination on average performs within 3% of ideal (zero-latency) synchronization, and achieves a speedup of 1.43X over the software (pthreads) implementation.
机译：尽管已经提出了许多硬件同步机制，但是当它们超过其硬件资源时它们要么不再起作用，要么遭受严重的性能损失，或者它们增加了显着的复杂性和处理这种资源溢出的成本。另外，现有的硬件同步建议集中于一种类型（屏障或锁）的同步，因此可能需要几种机制来支持实际应用程序，其中许多使用锁，屏障和/或条件变量。本文提出了MiSAR，一种支持所有三种常用同步类型（锁，屏障和条件变量）的简约同步加速器（MSA），以及一种动态管理其（非常）有限的硬件同步的新型溢出管理单元（OMU）。资源。 OMU允许在使用硬件（MSA）和软件同步实现之间进行安全有效的动态转换。这允许MSA的资源仅用于当前活动的同步操作，即使程序中使用的同步变量的数量远大于MSA的资源，也可提供显着的性能优势。因为它允许在硬件和软件同步之间进行安全的过渡，所以OMU还可促进线程挂起/恢复，迁移和其他线程管理活动。最终，MSA / OMU组合将指令集支持（程序如何调用硬件支持的同步）与加速器的实际实现脱钩，从而允许将来使用不同的加速器（甚至批量删除加速器）而无需更改OMU-兼容的应用程序或系统代码。我们显示，即使每个图块中只有2个MSA条目，MSA / OMU组合平均仍可以在理想（零延迟）同步的3％之内完成，与软件（pthreads）实现相比，可实现1.43倍的加速。

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