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首页> 外文会议>4th International Symposium on Bioelectronics and Bioinformatics >A compact multiply-accumulate architecture for clustering pulse-width coded biomedical signals
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A compact multiply-accumulate architecture for clustering pulse-width coded biomedical signals

机译：紧凑的乘法累加架构，用于对脉宽编码的生物医学信号进行聚类

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摘要

Analog-to-time conversion has been one alternative method of converting continuous-valued, biomedical signals into pulse-width-modulated (PWM) digital signals for reliable data transmission and signal processing. As most data classification algorithms rely on inner product with feature vectors, this paper presents a compact architecture for performing multiplication and accumulation on PWM signals. The proposed architecture contains a dual-scale counter (DSC) and a two-dimensional multiply-accumulate (2D-MAC) operator. The DSC converts a time-mode (PWM) signal to digital data containing one coarse-count value and one fine-count value. The 2D-MAC then performs a multiply-accumulate (MAC) operation based on the coarse-count and fine-count values. The full architecture has been realized in a field-programmable gate array (FPGA) for demonstration. A comparison of the proposed 2D-MAC operator with an 8 bit resolution MAC operator from the FPGA intellectual property library is also presented. Experimental results reveal that the 2D-MAC with DSC operator can reduce the chip area, while consumes compatible power with the FPGA IP library.
机译：模数转换是将连续值的生物医学信号转换为脉宽调制（PWM）数字信号以进行可靠的数据传输和信号处理的另一种方法。由于大多数数据分类算法都依赖于具有特征向量的内积，因此本文提出了一种紧凑的体系结构，用于对PWM信号执行乘法和累加。所提出的体系结构包含一个双尺度计数器（DSC）和一个二维乘法累加（2D-MAC）运算符。 DSC将时间模式（PWM）信号转换为包含一个粗略计数值和一个精细计数值的数字数据。然后，2D-MAC根据粗略计数值和精细计数值执行乘法累加（MAC）操作。完整的架构已在现场可编程门阵列（FPGA）中实现，以进行演示。还对提出的2D-MAC运算符与FPGA知识产权库中的8位分辨率MAC运算符进行了比较。实验结果表明，具有DSC运算符的2D-MAC可以减少芯片面积，同时消耗与FPGA IP库兼容的功耗。

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