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首页> 外文会议>8th International Workshop on Electromagnetic Compatibility of Integrated Circuits >Low-jitter frequency-modulated PLL: Clipped-FM PLL significantly reduces the maximum time interval error for proper operation of asynchronous serial data interfaces
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Low-jitter frequency-modulated PLL: Clipped-FM PLL significantly reduces the maximum time interval error for proper operation of asynchronous serial data interfaces

机译：低抖动调频PLL：限幅FM PLL大大减少了最大时间间隔误差，以确保异步串行数据接口的正常运行

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摘要

Frequency modulation of a clock is a well-known and efficient way to spread clock harmonics around a center frequency, thus reducing emitted narrow-band RF energy. While smoothly changing the clock periods, modulation continuously shifts the clock edges back and forth over a time interval determined by the modulation frequency. The resulting time interval error compared to an unmodulated clock may get so large that it violates the specification of commonly used asynchronous data protocols. This paper describes a modulation technique which manages to minimize the time interval error using a single modulated PLL clock. As a prove of concept, measurement results for jitter, electromagnetic emission and CAN communication are added and discussed.
机译：时钟的频率调制是一种众所周知的有效方式，可以在中心频率附近扩展时钟谐波，从而减少发射的窄带RF能量。在平稳地改变时钟周期的同时，调制在由调制频率确定的时间间隔内连续地来回移动时钟边沿。与未调制的时钟相比，最终的时间间隔误差可能会变得很大，以至于违反了常用异步数据协议的规范。本文介绍了一种调制技术，该技术使用单个调制的PLL时钟设法使时间间隔误差最小。作为概念的证明，增加并讨论了抖动，电磁辐射和CAN通信的测量结果。

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