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Achieving timing convergence between synthesis and place route

机译:实现综合与布局布线之间的时序收敛

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This paper compares the methodologies and results of three different approaches to achieving timing convergence between synthesis and place and route. First, we describe the traditional method of using synthesis and place and route tools individually while using either pessimistic wire loads or pessimistic constraints. Second, we describe the use of incremental optimization/implementation capabilities of front end and back end tools to achieve timing convergence. Last, we describe the use of timing driven place and route and place-ment-based optimization tools to achieve timing convergence.
机译:本文比较了三种不同方法在合成与布局和布线之间实现时序收敛的方法和结果。首先,我们描述了在使用悲观导线负载或悲观约束的情况下分别使用综合和布局布线工具的传统方法。第二,我们描述了前端和后端工具的增量优化/实现功能的使用,以实现时序收敛。最后,我们描述了使用时序驱动的布局和路线以及基于布局的优化工具来实现时序收敛。

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