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Design and Manufacture of Energy-Recycling Pads for Low-Power Chips

机译：低功耗芯片的能量回收垫的设计与制造

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Energy-recycling output pad cells for driving adiabatic chips are designed, which have been fabricated with Chartered 0.35um process and tested. The proposed energy-recycling output pad cells include mainly bonding pads, electrostatic discharge (ESD) protection circuits, and two stage energy-recycling buffers that are used to drive the large load capacitances on chip pads. The two stage energy-recycling buffers are realized using CPAL (Complementary Pass-transistor Adiabatic Logic) and PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration), respectively. For comparison, a conventional output pad cell is also embedded in the test chip. The function verifications and energy loss tests for the three output pad cells are carried out. The energy consumption of the proposed two energy-recycling output pad cells has large savings over a wide range of frequencies, as compared with the conventional CMOS counterparts, since the energy on large load capacitances in the chip pads can be well recycled.
机译：设计了用于驱动绝热芯片的能量回收输出焊盘单元，该结构已通过特许0.35um工艺制造并经过测试。提出的能量回收输出焊盘单元主要包括焊盘，静电放电（ESD）保护电路和两级能量回收缓冲器，用于驱动芯片焊盘上的大负载电容。两级能量回收缓冲器分别使用CPAL（互补式通过晶体管绝热逻辑）和PAL-2N（通过NMOS下拉配置的通过晶体管绝热逻辑）实现。为了比较，传统的输出焊盘单元也被嵌入在测试芯片中。对三个输出焊盘单元进行功能验证和能量损失测试。与传统的CMOS同类产品相比，建议的两个能量回收输出焊盘单元的能量消耗在较大的频率范围内节省了很多，因为芯片焊盘中大负载电容上的能量可以得到很好的回收。

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