An efficient architecture for hardware implementations of image processing algorithms

机译：用于图像处理算法的硬件实现的有效架构

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摘要

This work presents a new performance improvement technique for hardware implementations of non-recursive convolution based image processing algorithms. It combines an advanced data flow technique (instruction reuse) proposed in modern microprocessor design with the value locality of image data to develop a method, window memoization, that increases the throughput with minimal cost in area and accuracy. We implement window memoization as a 2-wide superscalar pipeline such that it consumes significantly less area than conventional 2-wide superscalar pipelines. As a case study, we have applied window memoization to Kirsch edge detector. The average speedup factor was 1.76 with only 25% extra hardware.

机译：这项工作提出了一种新的性能改进技术，用于基于非递归卷积的图像处理算法的硬件实现。它结合了现代微处理器设计中提出的高级数据流技术（指令重用）与图像数据的值局部性，从而开发了一种窗口便笺存储方法，以最小的面积和精度成本提高了吞吐量。我们将窗口记忆实现为2宽超标量管线，因此与传统的2宽超标量管线相比，它占用的面积大大减少。作为案例研究，我们将窗口记忆应用于Kirsch边缘检测器。平均加速因子为1.76，只有25％的额外硬件。

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来源
《Computational Intelligence for Image Processing, 2009. CIIP '09》|2009年|20-26|共7页
会议地点 Nashville TN(US);Nashville TN(US)
作者
Khalvati F.; Tizhoosh H.R.;
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Dept. of Syst. Design Eng., Univ. of Waterloo, Waterloo, ON;

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关键词
data flow computing; image processing; microprocessor chips; pipeline processing; 2-wide superscalar pipeline; data flow technique; hardware implementations; image processing algorithms; microprocessor design; nonrecursive convolution;

机译：数据流计算;图像处理;微处理器芯片;管道处理; 2维超标量流水线;数据流技术;硬件实现;图像处理算法;微处理器设计;非递归卷积;

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2. Efficient hierarchical matching algorithm for processing uncalibrated stereo vision images and its hardware architecture [J] . Nalpantidis L., Amanatiadis A., Sirakoulis G.C., Image Processing, IET . 2011,第5期

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3. On the design of optimal 2D filters for efficient hardware implementations of image processing algorithms by using power-of-two terms [J] . Hore Alain, Yadid-Pecht Orly Journal of Real-Time Image Processing . 2019,第2期

机译：关于使用2项幂的有效硬件实现图像处理算法的最佳2D滤波器的设计
4. AN EFFICIENT ARCHITECTURE FOR HARDWARE IMPLEMENTATIONS OF IMAGE PROCESSING ALGORITHMS [C] . Farzad Khalvati, Hamid R. Tizhoosh IEEE Symposium on Computational Intelligence for Image Processing . 2009

机译：用于图像处理算法的硬件实现的有效架构
5. Efficient design and implementation of image processing algorithms on reconfigurable hardware using Handel-C. [D] . Daggu, Venkateshwar Rao. 2003

机译：使用Handel-C在可重新配置的硬件上高效设计和实现图像处理算法。
6. Graphics Processing Unit (GPU) implementation of image processing algorithms to improve system performance of the Control Acquisition Processing and Image Display System (CAPIDS) of the Micro-Angiographic Fluoroscope (MAF) [O] . S.N. Swetadri Vasan, Ciprian N. Ionita, A.H. Titus, -1

机译：图形处理单元（GpU）执行的图像处理算法以改善控制采集处理的系统的性能以及微造影荧光镜的图像显示系统（CapIDs）（maF）
7. Efficient Processing Technique for Unavailable Data in Hardware Implementation of Motion Estimator with Parallel Processing Architecture [O] . Jong-Hwa Park, Hyun-Soo Kang 2009

机译：具有并行处理架构的运动估算硬件实现中不可用数据的高效处理技术

An efficient architecture for hardware implementations of image processing algorithms

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