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首页> 外文会议>Conference on advances in resist materials and processing technology XXVI; 20090223-25; San Jose, CA(US) >Improvements in process performance for immersion technology high volume manufacturing
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Improvements in process performance for immersion technology high volume manufacturing

机译：浸入技术大批量生产过程性能的改进

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Through collaborative efforts ASML and TEL are continuously improving the process performance for the LITHIUS Pro -i/ TWINSCAN XT:1900Gi litho cluster. In previous work from this collaboration, TEL and ASML have investigated the CDU and defectivity performance for the 45nm node with high through put processing. CDU performance for both memory and logic illumination conditions were shown to be on target for ITRS roadmap specifications. Additionally, it was shown that the current defect metrology is able to measure the required defect size of 30nm with a 90% capture rate. For the target through put of 180wph, no added impact to defectivity was seen from the multi-module processing on the LITHIUS Pro -i, using a topcoat resist process. For increased productivity, a new bevel cut strategy was investigated and shown to have no adverse impact while increasing the usable wafer surface. However, with the necessity of double patterning for at least the next technology node, more stringent requirements are necessary to prevent, in the worst case, doubling of the critical dimension variation and defectivity. In this work, improvements in process performance with regards to critical dimension uniformity and defectivity are investigated to increase the customer's productivity and yield for whichever double patterning scheme is utilized. Specifically, TEL has designed, evaluated and proven the capability of the latest technology hardware for post exposure bake and defect reduction. For the new post exposure bake hardware, process capability data was collected for 40nm CD targets. For defectivity reduction, a novel concept in rinse technology and processing was investigated on hydrophobic non top coat resists processes. Additionally, improvements to reduce micro bridging were evaluated. Finally bevel rinse hardware to prevent contamination of the immersion scanner was tested.
机译：通过协作，ASML和TEL不断提高LITHIUS Pro -i / TWINSCAN XT：1900Gi光刻机的工艺性能。在这项合作的先前工作中，TEL和ASML研究了具有高吞吐量处理能力的45nm节点的CDU和缺陷性能。对于ITRS路线图规范，在内存和逻辑照明条件下的CDU性能均已达到目标。此外，结果表明，当前的缺陷计量技术能够以90％的捕获率测量所需的30nm缺陷尺寸。对于180wph的目标吞吐率，使用面涂抗蚀剂工艺在LITHIUS Pro -i上进行的多模块处理不会对缺陷率产生额外影响。为了提高生产率，研究了一种新的斜切策略，该策略在增加可用晶片表面的同时没有不利影响。但是，由于至少在下一个技术节点上必须进行两次构图，因此在更坏的情况下，必须防止更严格的尺寸变化和缺陷率加倍，这一要求更为严格。在这项工作中，研究了在关键尺寸均匀性和缺陷性方面的工艺性能改进，以提高客户的生产率和良率，无论采用哪种双图案方案。具体地说，TEL已设计，评估并证明了最新技术硬件的能力，可用于后期曝光烘烤和减少缺陷。对于新的曝光后烘烤硬件，收集了40nm CD靶材的工艺能力数据。为了减少缺陷，在疏水性非面涂层抗蚀剂工艺上研究了漂洗技术和工艺中的新概念。另外，评估了减少微桥接的改进方法。最后，对斜面冲洗硬件进行了测试，以防止浸没扫描仪受到污染。

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