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首页> 外文会议>Conference on advances in resist materials and processing technology XXVI; 20090223-25; San Jose, CA(US) >Reducing LER using a grazing incidence ion beam
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Reducing LER using a grazing incidence ion beam

机译：使用掠入射离子束降低LER

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摘要

As semiconductor feature sizes and pitches shrink to ever-decreasing dimensions, Line Edge Roughness (LER) becomes and increasing important problem. The LER is transferred from the photoresist to the substrate through the subsequent processing steps, causing variations in, eg, gate length. This leads to mismatch in device performance and leakage. Thus, an efficient and cost effective way to reduce the LER in the semiconductor photoresist is needed in order to keep the imperfections from affecting processing steps further down the line. At the CPMI a new technique to reduce LER from patterened photoresist has been developed in conjunction with INTEL. Results obtained using our technique showed significant LER reduction from 6.9±0.47 nm to 3.9±0.61 nm for 45 nm lines and spaces. Recent results on 40 nm lines and spaces showed significant LER reduction from 5.9±0.50 nm to 4.1±0.63nm. LER reduction results on 40 nm lines and spaces reveal the fact that our technique is superior to other available techniques such as etching, vapor smoothing, hardbake, ozonation and rinse.
机译：随着半导体特征尺寸和节距缩小到不断减小的尺寸，线边缘粗糙度（LER）变得越来越重要。 LER通过随后的处理步骤从光致抗蚀剂转移到基板上，从而引起例如栅极长度的变化。这导致器件性能和泄漏不匹配。因此，需要一种有效且经济的方式来减小半导体光刻胶中的LER，以防止缺陷影响生产线的进一步加工。在CPMI上，与INTEL联合开发了一种新的技术，可以减少图案化光刻胶中的LER。使用我们的技术获得的结果表明，对于45 nm的线和间隔，LER的减小幅度从6.9±0.47 nm减小到3.9±0.61 nm。最近在40 nm线和间隔上的结果显示LER的降低幅度从5.9±0.50 nm降至4.1±0.63nm。在40 nm的线条和空间上的LER减少结果表明，我们的技术优于其他可用技术，例如蚀刻，蒸汽平滑，硬烤，臭氧化和冲洗。

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