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Data path allocation for low power in high-level synthesis

机译:高层综合中低功耗的数据路径分配

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摘要

This paper presents an approach for data path allocation in high-level synthesis aiming at power reduction. In this approach, the register allocation and module allocation are performed in the same phase in polynomial time. The power consumption is reduced by minimizing the functional switching activities and switched capacitance of the implementation architecture. The experimental results confirm the viability and usefulness of the approach in minimizing power consumption while keeping the number of registers and interconnections to the optimal.
机译:本文提出了一种旨在降低功耗的高级综合中的数据路径分配方法。在这种方法中,寄存器分配和模块分配在多项式时间内在同一阶段执行。通过最小化实现架构的功能性开关活动和开关电容来降低功耗。实验结果证实了该方法在最小化功耗的同时将寄存器和互连的数量保持在最佳状态的可行性和实用性。

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